yosys

Author	SHA1	Message	Date
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	0c6ffc4c65	More fixes for bugs found using xsthammer	2013-06-13 11:18:45 +02:00
Clifford Wolf	46fbe9d262	Added SAT generator and simple sat_solve command	2013-06-07 13:59:13 +02:00
Clifford Wolf	161565be10	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	2013-03-31 11:19:11 +02:00
Clifford Wolf	e45d1c8865	Tiny fixes to verilog parser	2013-03-23 18:54:31 +01:00
Clifford Wolf	4f0c2862a0	Added support for verilog genblock[index].member syntax	2013-02-26 13:18:22 +01:00
Clifford Wolf	6d1502b948	Added support for "always @(*)"	2013-01-16 17:32:11 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00