Commit Graph

4006 Commits

Author SHA1 Message Date
andyfox-rushc eccc0ae6db Based passes/techmap/Makefile.inc changes on latest in yosys 2023-09-11 12:14:12 -07:00
andyfox-rushc a2c8e47295 multpass.cc -> booth.cc, added author/support contact info 2023-09-11 11:39:13 -07:00
Martin Povišer 5bef9b4e75
Merge pull request #3915 from povik/sim-print
sim: Add print support
2023-09-11 17:03:59 +02:00
andyfox-rushc 1b5287af59 cpa_carry array added to heap 2023-09-10 14:20:30 -07:00
andyfox-rushc 8d4b6c2f69 Switched arrays for signed multiplier construction to heap 2023-09-10 13:31:47 -07:00
andyfox-rushc d77fb81507 2d array -> 1d array in module generator 2023-09-10 12:45:36 -07:00
andyfox-rushc 6d29dc659b renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script 2023-09-08 15:34:56 -07:00
andyfox-rushc 411acc4a0a Fixed edge size cases for signed/unsigned booth generator 2023-09-08 13:41:31 -07:00
andyfox-rushc fedefa26bc multpass -- create Booth Encoded multipliers for 2023-09-06 16:35:17 -07:00
Jannis Harder e187fc915e xprop: Fix polarity errors and generate hdlnames
* Fixes a non-deterministic polarity error for $eqx/$nex cells
* Fixes a deterministic polarity error for $_NOR_ and $_ORNOT_ cells
* Generates hdlnames when xprop is run after flatten
2023-09-06 19:25:47 +02:00
Martin Povišer d4d951657f sim: Add `-assert` option to fail on failed assertions 2023-09-05 10:46:04 +02:00
Martin Povišer e995dddeaa abc: Warn about replacing undef bits 2023-09-05 10:45:30 +02:00
Martin Povišer c6566b660f memlib.md: Fix typo 2023-09-04 17:38:35 +02:00
Martin Povišer 3de84b959f memory_libmap: Tweak whitespace 2023-09-04 17:38:35 +02:00
Martin Povišer 50d117956c sim: Add print support 2023-09-04 17:12:38 +02:00
Miodrag Milanovic a8809989c4 ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech 2023-08-22 10:50:11 +02:00
Ethan Mahintorabi d525a41497
abc: Exposes dont_use flag in ABC
ABC's read_lib command has a dont_use
cell list that is configurable by the user.

This PR exposes that option to Yosys.

See
5405d4787a/src/map/scl/scl.c (L285)
for documentation on this option.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2023-08-15 20:03:46 +00:00
Charlotte 860e3e4056 proc_clean: only consider fully-defined switch operands too. 2023-08-12 02:46:31 +02:00
Charlotte bf84861fc2 proc_clean: only consider fully-defined case operands. 2023-08-12 02:46:31 +02:00
whitequark d51ecde8c2 clean: keep $print cells, since they have unmodelled side effects. 2023-08-11 04:46:52 +02:00
Martin Povišer ff3c7873f5 wreduce: Group reconnections
Group the reconnections, so that instead of producing

  connect $auto$wreduce.cc:455:run$24 [0] 1'0
  connect $auto$wreduce.cc:455:run$23 [31] 1'0
  connect $auto$wreduce.cc:455:run$23 [30] 1'0
  ... (40 more lines)

we produce

  connect $auto$wreduce.cc:461:run$23 [31:11] 21'000000000000000000000
  connect $auto$wreduce.cc:461:run$24 [31:10] 22'0000000000000000000000

.
2023-08-04 14:43:59 +01:00
Martin Povišer f8325f66b7 opt_expr: Fix 'signed X>=0' replacement for wide output ports
If the `$ge` cell we are replacing has wide output port, the upper bits
on the port should be driven to zero. That's not what a `$not` cell with
a single-bit input does. Instead opt for a `$logic_not` cell, which does
zero-pad its output.

Fixes #3867.
2023-08-01 13:50:12 +01:00
N. Engelhardt 43780c9812
Merge pull request #3838 from povik/various-cleanup 2023-07-24 16:24:23 +02:00
Catherine 6965abeefa abc, abc9_exe: fix build on WASI (and others with `const* stdout`).
C does not guarantee that stdout/stderr can be reassigned.
Most platforms do make them assignable, however musl and WASI that
is based on musl do not. WASI does not have `dup2()`; instead it has
its own non-portable version of it that can only assign to previously
allocated fds.

Update the stream redirection code so that it does the right thing
on WASI and other platforms.
2023-07-23 05:13:29 +01:00
Catherine 411b6e98cd abc, abc9_exe: respect `-q` when built with linked ABC.
This is mostly important for YoWASP builds, since those do not have
a way to build with external ABC (I prototyped it but for some reason
ABC always segfaults when built as an independent Wasm binary...)
2023-07-23 02:03:29 +01:00
Martin Povišer f5485b59a9 sim: Bail if there are blackboxes in simulation 2023-07-20 21:01:03 +01:00
Martin Povišer f0ae046c5a opt_share: Fix input confusion with ANDNOT, ORNOT gates
Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_`
gates when considering those for sharing. Unlike the input ports of the
other supported single-bit gates, those are not interchangeable.

Fixes #3848.
2023-07-20 20:58:52 +01:00
N. Engelhardt 2be5c0786f
Merge pull request #3826 from nakengelhardt/nak/mem_libmap_print_attr 2023-07-17 16:35:10 +02:00
Martin Povišer eb083c5d4b extract_counter: Update help and comments after UP/DOWN support
Commit fec7dc5c should have added support for up counters so update
the help and comments accordingly.
2023-07-10 12:45:03 +02:00
N. Engelhardt 57de249881 memory_libmap: print additional debug messages when no valid mapping is found 2023-07-06 18:54:32 +02:00
N. Engelhardt 14d50a176d
Merge pull request #3676 from nakengelhardt/dfflegalize_scratchpad_minarg 2023-07-03 17:15:21 +02:00
N. Engelhardt a6be7b4751 memory_libmap: add debug messages for some reasons for rejecting mappings 2023-06-29 14:08:31 +02:00
N. Engelhardt 7542146fc5 memory_libmap: print message about attributes forcing ram kind 2023-06-28 17:48:20 +02:00
Jannis Harder a07f8ac38a check: Also check for conflicts with constant drivers 2023-06-23 18:07:28 +02:00
Claire Xen 51e627686a
Merge pull request #3812 from charlottia/iterator-invalidation
proc_prune: avoid using invalidated iterator
2023-06-21 14:46:25 +02:00
Charlotte 63e4114233 proc_prune: avoid using invalidated iterator
An `std::vector<T>::reverse_iterator` stores the
`std::vector<T>::iterator` which points to the (forwards-ordered)
*following* item.  Thus while `vec.rbegin()` dereferences to the final
item of `vec`, the iterator it wraps (`vec.rbegin().base()`) is equal to
`vec.end()`.

In the remove case here, we advance `it` (backwards), erasing the item
we just advanced past by grabbing its (pre-increment) base
forward-iterator and subtracting 1.

The iterator maths here is obviously all OK, but the forward-iterator
that `it` wraps post-increment actually points to the item we just
removed.  That iterator was invalidated by the `erase()` call.

That this works anyway is (AFAICT) some combination of luck and/or
promises that aren't part of the C++ spec, but MSVC's debug iterator
support picks this up.

`erase()` returns the new iterator that follows the item just erased,
which happens to be the exact one we want our reverse-iterator to wrap
for the next loop; we get a fresh iterator to the same base, now without
the preceding item.
2023-06-21 19:53:08 +10:00
N. Engelhardt 9c7f0e7670 show: truncate very long module names 2023-06-20 12:53:56 +02:00
N. Engelhardt 22c9237716 show: escape angle brackets 2023-06-20 11:17:12 +02:00
N. Engelhardt 7c606bd5a3
Merge pull request #3791 from nakengelhardt/nak/show_attr_wires 2023-06-05 16:18:54 +02:00
N. Engelhardt 6f5d984bdb
Merge pull request #3778 from jix/yw_clk2fflogic 2023-06-05 16:15:04 +02:00
N. Engelhardt 0707b911c7 show: add -viewer none option 2023-06-01 11:00:07 +02:00
N. Engelhardt 4b986c9c65 fix wire color after BUF 2023-05-31 17:38:46 +02:00
N. Engelhardt 26555a998d show -colorattr: extend colors to arrows when wires have attribute 2023-05-26 17:18:21 +02:00
Eddie Hung ec8d7b1c68 abc9_ops -prep_hier to unmap entire module 2023-05-25 18:42:08 +01:00
Jannis Harder e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses
This makes clk2fflogic add an attr to $ff cells that carry the state of
the emulated async FF. The $ff output doesn't have any async updates
that happened in the current cycle, but the $ff input does, so the $ff
input corresponds to the async FF's output in the original design.

Hence this patch also makes the following changes to passes besides
clk2fflogic (but only for FFs with the clk2fflogic attr set):

  * opt_clean treats the input as a register name (instead of the
    output)

  * rename -witness ensures that the input has a public name

  * the formal backends (smt2, btor, aiger) will use the input's
    name for the initial state of the FF in witness files

  * when sim reads a yw witness that assigns an initial value to the
    input signal, the state update is redirected to the output

This ensures that yosys witness files for clk2fflogic designs have
useful and stable public signal names. It also makes it possible to
simulate a clk2fflogic witness on the original design (with some
limitations when the original design is already using $ff cells).

It might seem like setting the output of a clk2fflogic FF to update the
input's initial value might not work in general, but it works fine for
these reasons:

  * Witnesses for FFs are only present in the initial cycle, so we do
    not care about any later cycles.

  * The logic that clk2fflogic generates loops the output of the
    genreated FF back to the input, with muxes in between to apply any
    edge or level sensitive updates. So when there are no active updates
    in the current gclk cycle, there is a combinational path from the
    output back to the input.

  * The logic clk2fflogic generates makes sure that an edge sensitive
    update cannot be active in the first cycle (i.e. the past initial
    value is assumed to be whatever it needs to be to avoid an edge).

  * When a level sensitive update is active in the first gclk cycle, it
    is actively driving the output for the whole gclk cycle, so ignoring
    any witness initialization is the correct behavior.
2023-05-25 12:48:02 +02:00
Jannis Harder 7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization 2023-05-25 12:46:16 +02:00
gatecat 52c8c28d2c Add recover_names pass to recover names post-mapping 2023-05-25 10:55:07 +02:00
Jannis Harder ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs
When assigning values to input ports of nested modules in cosimulation,
sim needs to find the actual driver of the signal to perform the
assignment. The existing code didn't handle unconnected inputs in that
scenario.
2023-05-18 16:50:11 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை) 693c609eec
Merge branch 'YosysHQ:master' into main/issue2525 2023-05-16 21:21:32 -07:00
Muthu Annamalai 665e0f6131 remove new line per maintainer request 2023-05-17 04:20:13 +00:00
Miodrag Milanović acfdc5cc42
Merge pull request #3755 from RTLWorks/muthu/issue3498
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
2023-05-15 16:34:35 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை) c855502bd5
Update passes/techmap/libparse.cc
Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498

Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
2023-05-09 06:40:21 -07:00
Miodrag Milanović 226a224640
Merge pull request #3749 from lethalbit/aki/plugin-stuff
Updated the `plugin` command to better handle paths
2023-05-09 08:46:02 +02:00
N. Engelhardt 266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback 2023-05-08 16:21:24 +02:00
N. Engelhardt ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames 2023-05-08 16:13:28 +02:00
Krystine Sherwin 5a4e72f57a
Fix sim writeback check for yw_cosim
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
2023-05-08 13:13:09 +12:00
Muthu Annamalai 17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest 2023-05-06 23:37:47 -07:00
Miodrag Milanović 4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop
Synthesizable properties
2023-05-05 11:03:09 +02:00
Muthu Annamalai 81e089cb60 [YOSYS-2525] fix read_liberty newline handling #2525
- newlines can be allowed in function parsing
2023-05-04 22:30:27 -07:00
Aki Van Ness bb240665b7
plugin: shuffled the `#ifdef WITH_PYTHON`'s around to un-tangle the code and pulled out the check for the `.py` extension so it will complain if you try to load a python extension without python support 2023-05-03 03:35:55 -04:00
Aki Van Ness 572c8df9a8
plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with `.so.so` on the end 2023-05-03 02:22:46 -04:00
Jannis Harder 7bff8b63b3 rename: Fix renaming cells in -witness mode
This was renaming cells while iterating over them which would always
cause an assertion failure. Apparently having to rename cells to make
all witness signals public is rarely required, so this slipped through.
2023-04-25 12:39:00 +02:00
Benjamin Barzen 8611429237
ABC9: Cell Port Bug Patch (#3670)
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2023-04-22 16:24:36 -07:00
N. Engelhardt 57897927ff stat: pass down quiet arg 2023-02-28 17:12:55 +01:00
Miodrag Milanović 21e87f7986
Merge pull request #3646 from YosysHQ/lofty/fix-3591
muxcover: do not add decode muxes with x inputs
2023-02-27 16:26:57 +01:00
Jannis Harder 1c667fab2b
Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes
sim: For yw cosim, drive parent module's signals for input ports
2023-02-15 13:45:00 +01:00
N. Engelhardt b562b54c14 dfflegalize: allow setting mince and minsrst args from scratchpad 2023-02-15 12:53:46 +01:00
Jannis Harder ec94703619
Merge pull request #2995 from georgerennie/cover_precond
chformal: Add -coverenable option
2023-02-14 17:46:31 +01:00
Jannis Harder 85f611fb23
Merge pull request #3126 from georgerennie/equiv_make_assertions
equiv_make: Add -make_assert option
2023-02-14 17:15:55 +01:00
Jannis Harder b636af9751 chformal: Note about using -coverenable with the Verific frontend 2023-02-14 17:10:43 +01:00
Miodrag Milanovic 550a5b7b6b Update license 2023-02-13 17:23:26 +01:00
Miodrag Milanovic 713b7d3e26 added support for latched output reset 2023-02-13 17:23:26 +01:00
Miodrag Milanovic 131b557727 Initial implementation of synthesizable assertions 2023-02-13 17:23:26 +01:00
Jannis Harder 1698202ccc sim: For yw cosim, drive parent module's signals for input ports 2023-02-13 12:26:06 +01:00
Miodrag Milanovic 5f33c0e0b2 Updated changelog 2023-02-08 10:11:47 +01:00
N. Engelhardt 417fadbefd
Merge pull request #3625 from povik/show_cleanup 2023-02-06 16:11:26 +01:00
N. Engelhardt 419f91a2b9 add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
N. Engelhardt ecfa7e9fbc add pmux option to bmuxmap for better fsm detection with verific frontend 2023-01-30 16:12:53 +01:00
Lofty 822c7b0341 muxcover: do not add decode muxes with x inputs 2023-01-26 05:19:45 +00:00
Jannis Harder afac3f2c76 formalff: Fix crash with _NOT_ gates in -hierarchy mode 2023-01-25 12:55:29 +01:00
Miodrag Milanović 8180cc4325
Merge pull request #3624 from jix/sim_yw
Changes to support SBY trace generation with the sim command
2023-01-23 16:55:17 +01:00
Miodrag Milanović 245884a101
Merge pull request #3629 from YosysHQ/micko/clang_fixes
Fixes for some of clang scan-build detected issues
2023-01-23 16:24:22 +01:00
gatecat bfacaddca8 show: Remove left-in debug log_warning
Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-23 13:54:07 +01:00
Claire Xenia Wolf bfc3c20cfb Improve splitcells pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-01-18 00:31:29 +01:00
Miodrag Milanovic 6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Martin Povišer f9e30ee5e0 passes: show: s/pos/bitpos/ for readability
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 314b864205 passes: show: Reuse string parts in generation of portboxes
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 61abca10a3 passes: show: Touch chunk iteration in gen_portbox
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 60318a5cd8 passes: show: Label no_signode flag
Label the flag and rearrange the control flow a bit.

Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 8b1f5fba62 passes: show: Simplify wire bit range logic
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer ad149cc42a passes: show: Factor out 'join_label_pieces'
In two places, we are joining label pieces by a '|' separator. We go
about it by putting the separator behind each entry, then removing the
trailing separator in a final fixup pass on the built string. For easier
reading, replace those occurrences by a new factored-out
'join_label_pieces' function.

Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 5848790835 passes: show: Label signed_suffix flag
To make it easier to follow what's going on.

Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer 13700e12e5 passes: show: s/idx/dot_idx/ for readability
Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Martin Povišer e3709ce776 passes: show: Fix portbox bit ranges in case of driven signals
When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.

So, taking for example the following Verilog snippet,

  module DRIVER (Q);
     output [7:0] Q;
     assign Q = 8'b10101010;
  endmodule

  module main;
     wire w;
     DRIVER driver(.Q({8{w}}));
  endmodule

make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.

Signed-off-by: Martin Povišer <povik@cutebit.org>
2023-01-13 19:57:24 +01:00
Jannis Harder d6c7aa0e3d sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
Jannis Harder 7ddec5093f sim: Improvements and fixes for yw cosim
* Fixed $cover handling
  * Improved sparse memory handling when writing traces
  * JSON summary output
2023-01-11 18:07:16 +01:00
Jannis Harder dda972a148 sim: New -append option for Yosys witness cosim
This is needed to support SBY's append option.
2023-01-11 18:07:16 +01:00
Jannis Harder 2dd5652215 sim: Add Yosys witness (.yw) cosimulation 2023-01-11 18:07:16 +01:00
Jannis Harder f6458bab70 sim: Only check formal cells during gclk simulation updates
This is required for compatibility with non-multiclock formal semantics.
2023-01-11 18:07:16 +01:00
Jannis Harder 9c6198a827 sim: Internal API to set $initstate
This is not yet added to any of the simulation drivers.
2023-01-11 18:07:16 +01:00
Jannis Harder 44b26d5c6d sim: Emit used memory addresses as signals to output traces
This matches the behavior of smtbmc.

This also updates the sim internal memory API to allow masked writes
where State::Sa bits (internal don't care - not a valid value for a
signal) leave the memory content unchanged.
2023-01-11 18:07:16 +01:00
Jannis Harder 5042600c0d xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef
This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
2023-01-11 18:07:16 +01:00
N. Engelhardt 4173daa708
Merge pull request #3605 from gadfort/stat-json-area 2023-01-11 16:41:44 +01:00
Claire Xen 843f329b96
Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop
New xprop pass
2023-01-11 16:26:04 +01:00
Miodrag Milanovic 5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Claire Xenia Wolf 6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00
Miodrag Milanovic e3c0fd8b10 qbfsat support for cvc5, fixes #3608 2023-01-09 16:14:01 +01:00
Peter Gadfort 58cca9592d stat: ensure area is included in json output
Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
2022-12-29 21:51:46 -05:00
Claire Xenia Wolf 029b0aac7f Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-21 14:50:23 +01:00
Claire Xenia Wolf 1bc832a8e1 Allow non-unique modules without state in sim writeback-mode
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-21 10:43:02 +01:00
Claire Xenia Wolf a9072dc23c Small bugfix in uniquify pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-21 10:41:48 +01:00
Jannis Harder 4a0ed35aab xprop: Improve signal splitting code
Avoid splitting output ports twice when combining -split-outputs with
-split-public and clean up the corresponding code.
2022-12-12 17:51:01 +01:00
Claire Xenia Wolf 6a6e1d8424 Improvements in "viz" pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-09 18:28:17 +01:00
Jannis Harder 967529abb1 formalff: Proper error messages on async inputs for the -clk2ff mode 2022-12-09 15:25:40 +01:00
Claire Xenia Wolf dc14def5f3 Add gold-x handing to miter cross port handling
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-08 22:14:16 +01:00
Claire Xenia Wolf 3454bddbe2 Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-08 20:06:23 +01:00
Jannis Harder 172a8e79f0 xprop: Add -split-public option 2022-12-08 20:00:01 +01:00
Claire Xenia Wolf 068031d2aa Improvements in "viz" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-07 16:10:58 +01:00
Claire Xenia Wolf aeba966475 Improvements in "viz" pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-07 12:46:49 +01:00
Claire Xenia Wolf c679b408cb Various improvements in "viz" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-06 16:43:01 +01:00
Claire Xenia Wolf 2895a66784 Bugfix in splitcells pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-06 16:00:48 +01:00
Claire Xenia Wolf e151e44caa Improvements in "viz" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 19:32:31 +01:00
Claire Xenia Wolf c9f4b06cb2 Add "viz" pass for visualizing big-picture data flow in larger designs
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 11:35:10 +01:00
Claire Xenia Wolf 92fc6cd4a9 Add splitcells pass
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-04 01:33:04 +01:00
Jannis Harder 7036a312bf stat: Fix JSON output for empty designs 2022-12-02 14:36:19 +01:00
Jannis Harder ed02d52f30 tee: Allow logging command output to a given scratchpad value 2022-12-02 14:36:19 +01:00
Claire Xenia Wolf 956b7f5fd1 Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuff 2022-12-01 11:31:39 +01:00
Claire Xenia Wolf fbf8bcf38f Add insbuf -chain mode
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-12-01 10:02:35 +01:00
Jannis Harder eb0039848b miter: Add -make_cover option to cover each output pair difference 2022-11-30 19:01:28 +01:00
Jannis Harder 551ca7f97f formalff: Fix -ff2anyinit assertion error for fine FFs 2022-11-30 19:01:28 +01:00
Jannis Harder ce708122a5 New xprop pass to encode 3-valued x-propagation using 2-valued logic 2022-11-30 19:01:28 +01:00
Jannis Harder 5ff69a0fe2 sim: Improved global clock handling 2022-11-30 18:50:53 +01:00
Jannis Harder 3ecf85e32c opt_expr: Optimizations for `$bweqx` and `$bwmux` 2022-11-30 18:50:53 +01:00
Jannis Harder be752a20dc Add bwmuxmap pass 2022-11-30 18:50:53 +01:00
Jannis Harder 7203ba7bc1 Add bitwise `$bweqx` and `$bwmux` cells
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
2022-11-30 18:24:35 +01:00
Jannis Harder 1e67c3a3c2 opt_expr: Fix shift/shiftx optimizations 2022-11-30 18:24:25 +01:00
Jannis Harder fd56d1f79e opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells 2022-11-29 19:06:45 +01:00
Jannis Harder c08242ba41 opt_expr: Optimize bitwise logic ops with one fully const input 2022-11-29 19:06:45 +01:00
Jannis Harder 661fa5ff92 simplemap: Map `$xnor` to `$_XNOR_` cells
The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
2022-11-29 19:06:45 +01:00
Jannis Harder ed0e14820e sat: Add -set-def-formal option to force defined $any* outputs 2022-11-28 14:50:52 +01:00
Miodrag Milanovic b0be19c126 Support importing verilog configurations using Verific 2022-11-25 13:02:11 +01:00
N. Engelhardt b64141f48b mention prerequisites in fsm_detect and fsm help 2022-11-21 16:07:23 +01:00
KrystalDelusion a14dec79eb
Rst docs conversion (#3496)
Rst docs conversion
2022-11-15 12:55:22 +01:00
Jannis Harder 9b4fba3870 sim: Run a comb-only update step to set past values during FST cosim
The previous approach only initialized past_d and past_ad while for FST
cosim we also need to initialize the other past values like past_clk,
etc. Also to properly initialize them, we need to run a combinational
update step in case any of the wires feeding into the FF are private or
otherwise not part of the FST.
2022-11-07 14:09:33 +01:00
Claire Xenia Wolf a4eb7e41c0 Add extra time at the end of a sat VCD trace
Otherwise the final values will not show up in gtkwave waveforms
when looking at the generated traces.

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-11-01 17:51:46 +01:00
Claire Xenia Wolf d04c17fd58 Add miter -cross option 2022-10-24 23:23:33 +02:00
Jannis Harder c77b7343d0 Consistent $mux undef handling
* Change simlib's $mux cell to use the ternary operator as $_MUX_
  already does
* Stop opt_expr -keepdc from changing S=x to S=0
* Change const eval of $mux and $pmux to match the updated simlib
  (fixes sim)
* The sat behavior of $mux already matches the updated simlib

The verilog frontend uses $mux for the ternary operators and this
changes all interpreations of the $mux cell (that I found) to match the
verilog simulation behavior for the ternary operator. For 'if' and
'case' expressions the frontend may also use $mux but uses $eqx if the
verilog simulation behavior is requested with the '-ifx' option.

For $pmux there is a remaining mismatch between the sat behavior and the
simlib behavior. Resolving this requires more discussion, as the $pmux
cell does not directly correspond to a specific verilog construct.
2022-10-24 12:03:01 +02:00
Claire Xenia Wolf 0516307637 Add "check -assert" to equiv_opt
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-10-07 16:04:51 +02:00
Claire Xenia Wolf afa5e6bb53 Exclude primary inputs from quiv_make rewiring
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2022-10-07 16:04:51 +02:00