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Commit Graph

Author	SHA1	Message	Date
Marcin Kościelnicki	aff6ad1ce0	xilinx: Improve flip-flop handling. This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.	2019-12-18 13:43:43 +01:00
Marcin Kościelnicki	4535f2c694	synth_xilinx: Support latches, remove used-up FF init values. Fixes #1387.	2019-09-30 12:52:43 +02:00
Marcin Kościelnicki	fda94311ee	synth_xilinx: Support init values on Spartan 6 flip-flops properly.	2019-09-07 16:30:43 +02:00

Author

SHA1

Message

Date

Marcin Kościelnicki

aff6ad1ce0

xilinx: Improve flip-flop handling.

This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.

2019-12-18 13:43:43 +01:00

Marcin Kościelnicki

4535f2c694

synth_xilinx: Support latches, remove used-up FF init values.

Fixes #1387.

2019-09-30 12:52:43 +02:00

Marcin Kościelnicki

fda94311ee

synth_xilinx: Support init values on Spartan 6 flip-flops properly.

2019-09-07 16:30:43 +02:00

3 Commits