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11962 Commits

Author SHA1 Message Date
Miodrag Milanović 2a76af9eb6
Merge pull request #3263 from YosysHQ/micko/clk2ff_init 
Set init values for wrapped  async control signals
 2022-04-01 19:37:02 +02:00
Miodrag Milanovic 86ce441af6 Set init values for wrapped async control signals 2022-04-01 17:44:00 +02:00
Miodrag Milanović 2ec4af56e6
Merge pull request #3262 from YosysHQ/micko/verific_hiernet 
Preserve internal wires for external nets
 2022-04-01 12:58:09 +02:00
Miodrag Milanovic 1a1f529099 Preserve internal wires for external nets 2022-04-01 12:07:15 +02:00
github-actions[bot] 2b115d858d Bump version 2022-04-01 01:25:19 +00:00
Miodrag Milanović ed83f0dea8
Merge pull request #3256 from YosysHQ/micko/aiw_multiclock 
Support memories in aiw and multiclock
 2022-03-31 15:45:30 +02:00
Miodrag Milanovic c95b9b4ba5 Support memories in aiw and multiclock 2022-03-31 13:10:13 +02:00
github-actions[bot] fc2af4e32d Bump version 2022-03-31 01:15:49 +00:00
Miodrag Milanović 18fb73fd89
Merge pull request #3259 from YosysHQ/micko/verific_valgrind 
Fix valgrind tests when using verific
 2022-03-30 17:29:40 +02:00
Miodrag Milanovic bbf65702a1 Fix valgrind tests when using verific 2022-03-30 17:25:53 +02:00
Miodrag Milanović 0921e5b9a4
Merge pull request #3260 from YosysHQ/micko/proper_scopename 
Proper scope naming from FST
 2022-03-30 16:51:27 +02:00
Miodrag Milanovic 2e47b61cc6 Proper scope naming from FST 2022-03-30 15:55:15 +02:00
Miodrag Milanović 72e5498bdf
Merge pull request #3250 from YosysHQ/micko/verific_consistent 
Import Verific netlist in consistent order
 2022-03-30 11:03:14 +02:00
github-actions[bot] c662fcbc5c Bump version 2022-03-30 01:17:20 +00:00
Miodrag Milanović d44f618de5
Merge pull request #3258 from jix/fix-no-assertions 
smtbmc: fix bmc with no assertions
 2022-03-29 21:20:07 +02:00
Jannis Harder 8b15f3a548 smtbmc: fix bmc with no assertions 
this was broken by the `--keep-going` changes
 2022-03-29 20:41:50 +02:00
github-actions[bot] 48d7a6c477 Bump version 2022-03-29 00:16:12 +00:00
Marcelina Kościelnicka 3bebe17e5d kernel/mem: Only use FF init in read-first emu for mem with init 2022-03-28 17:03:02 +02:00
Jannis Harder 8cc8c5efde
Merge pull request #3253 from jix/smtbmc-nodeepcopy 
smtbmc: Avoid unnecessary deep copies during unrolling
 2022-03-28 16:59:26 +02:00
Jannis Harder 17e2a3048c
Merge pull request #3247 from jix/smtbmc-keepgoing 
smtbmc `--keep-going`
 2022-03-28 16:58:41 +02:00
Lofty c1057cb3e0
Merge pull request #3194 from Ravenslofty/abc9-flow3mfs 
abc9: add flow3mfs script
 2022-03-28 15:51:04 +01:00
Lofty 421192f1cb
Merge pull request #3246 from YosysHQ/gatecat/timing-derive-fix 
abc9_ops: Also derive blackboxes with timing info
 2022-03-28 15:50:53 +01:00
Tim Pambor 30bc0d26ea gowin: Add oscillator primitives 2022-03-28 13:33:24 +02:00
Jannis Harder d25daa6203 smtbmc: Avoid unnecessary deep copies during unrolling 2022-03-28 13:03:48 +02:00
Miodrag Milanović 62b89bb0d4
Update URL to zlib 2022-03-28 11:05:30 +02:00
Miodrag Milanovic 703769e494 Properly mark modules imported 2022-03-26 09:43:51 +01:00
github-actions[bot] 207417617d Bump version 2022-03-26 00:13:30 +00:00
NotAFile 349c0ff0a7 Add some more reserve calls to RTLIL::Const 
This results in a slight ~0.22% total speedup synthesizing vexriscv
 2022-03-25 18:38:00 +00:00
Miodrag Milanović a7e7a9f485
Merge pull request #3249 from YosysHQ/micko/no_startoffset 
Add -no-startoffset option to write_aiger
 2022-03-25 14:29:21 +01:00
Miodrag Milanovic 245ecb0529 Import verific netlist in consistent order 2022-03-25 13:44:16 +01:00
Miodrag Milanovic 4fd8b38d7a Add -no-startoffset option to write_aiger 2022-03-25 08:44:45 +01:00
github-actions[bot] afe258e6f8 Bump version 2022-03-25 00:13:36 +00:00
Miodrag Milanović 89dcd7c31e
Merge pull request #3243 from nakengelhardt/fix_aiw_comment 
smtbmc: ignore # comment lines
 2022-03-24 17:25:09 +01:00
Jannis Harder 5e4d804e53 yosys-smtbmc: Option to keep going after failed assertions in BMC mode 2022-03-24 16:01:14 +01:00
Jannis Harder e43ebf8527 yosys-smtbmc: Fix typo in help text, remove trailing whitespace 2022-03-24 16:01:14 +01:00
gatecat 8b64dc1dce abc9_ops: Also derive blackboxes with timing info 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-24 14:36:07 +00:00
N. Engelhardt a7ee01065a ignore # comment lines 2022-03-24 10:19:17 +01:00
github-actions[bot] 6318db6152 Bump version 2022-03-23 00:14:55 +00:00
Miodrag Milanovic 15c7205908 Update abc with latest fix 2022-03-22 18:47:48 +01:00
Miodrag Milanovic 322ab1cd54 Proper SigBit forming in sim 2022-03-22 14:43:18 +01:00
Miodrag Milanovic ff3b0c2c46 Proper SigBit forming in sim 2022-03-22 14:22:32 +01:00
github-actions[bot] f45b290820 Bump version 2022-03-22 00:15:19 +00:00
Marcelina Kościelnicka be9595e18f xilinx: Add RAMB4* blackboxes 2022-03-21 13:11:52 +01:00
github-actions[bot] 3bf1070245 Bump version 2022-03-19 00:12:57 +00:00
Miodrag Milanovic 55eed8df57 More verbose warnings 2022-03-18 14:47:35 +01:00
Miodrag Milanović 0c5279b73d
Merge pull request #3236 from YosysHQ/micko/tb_initial 
Recognize registers and set initial state for them in tb
 2022-03-17 17:15:36 +01:00
github-actions[bot] e1d4863a19 Bump version 2022-03-17 00:13:12 +00:00
Miodrag Milanovic 1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic e217e3017a Update sim help message. 2022-03-16 07:55:57 +01:00
github-actions[bot] 66914b6eb3 Bump version 2022-03-15 01:09:43 +00:00