riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,324 Commits 87 Branches 48 Tags 38 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Marcin Kościelnicki 30854b9c7f xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00