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10324 Commits

Author SHA1 Message Date
Yosys Bot 58e8901fee Bump version 2020-11-17 00:10:06 +00:00
William Woodruff c7cf9415f8
backends/blif: Remove unused vector of strings (#2420) 
* backends/blif: Remove unused vector of strings

For reasons that are unclear to me, this was being used to store every
result of `cstr` before returning them. The vector was never accessed otherwise,
resulting in a huge unnecessary memory sink when emitting to BLIF.

* backends/blif: Remove CSTR macro

* backends/blif: Actually call str()
 2020-11-16 09:31:48 +01:00
Miodrag Milanović 2ee5db0211
Merge pull request #2438 from kbeckmann/gowin_rpll 
synth_gowin: Add rPLL blackbox
 2020-11-16 09:30:54 +01:00
Konrad Beckmann 5b9a975eba synth_gowin: Add rPLL blackbox 2020-11-11 17:06:54 +01:00
Yosys Bot 71ca9a8253 Bump version 2020-11-11 00:10:17 +00:00
Miodrag Milanović 924f1713c2
Merge pull request #2433 from YosysHQ/paths_as_globals 
Expose abc and data paths as globals for pyosys
 2020-11-10 08:05:42 +01:00
Yosys Bot 014c7e26b8 Bump version 2020-11-08 00:10:06 +00:00
whitequark 630be7e11a
Merge pull request #2414 from zeldin/abc-depend-clang-fix 
Prevent CXXFLAGS from leaking to abc Makefile
 2020-11-07 18:48:03 +00:00
Marcus Comstedt 5594594e16 Prevent CXXFLAGS from leaking to abc Makefile 
This fixes an issue with abc/depends.sh when the compiler is clang.
 2020-11-07 16:02:49 +01:00
Miodrag Milanović 6940ef933a
Merge pull request #2432 from Xiretza/nexus-tests 
Update nexus arch tests to new harness
 2020-11-07 15:07:45 +01:00
Miodrag Milanovic 829b5cca60 Expose abc and data paths as globals 2020-11-06 14:17:15 +01:00
Yosys Bot e7f36d01e4 Bump version 2020-11-03 00:10:05 +00:00
whitequark c9e6a5b854
Merge pull request #2426 from whitequark/cxxrtl-auto-top 
cxxrtl: run `hierarchy -auto-top` if no top module is present
 2020-11-02 20:58:10 +00:00
whitequark 65083e9520 cxxrtl: run `hierarchy -auto-top` if no top module is present. 
In most cases, a CXXRTL simulation would use a top module, either
because this module serves as an entry point to the CXXRTL C API,
or because the outputs of a top module are unbuffered, improving
performance. Taking this into account, the CXXRTL backend now runs
`hierarchy -auto-top` if there is no top module. For the few cases
where this behavior is unwanted, it now accepts a `-nohierarchy`
option.

Fixes #2373.
 2020-11-02 19:18:56 +00:00
Yosys Bot d9af3cadf8 Bump version 2020-11-02 00:10:06 +00:00
whitequark bbaf8693c6
Merge pull request #2425 from whitequark/cxxrtl-meminit-constness 
cxxrtl: don't assert on non-constant $meminit inputs
 2020-11-01 17:08:42 +00:00
whitequark 2ba05f5c31 cxxrtl: don't assert on non-constant $meminit inputs. 
Fixes #2129.
 2020-11-01 15:57:20 +00:00
whitequark cc7ad65a79
Merge pull request #2424 from whitequark/cxxrtl-multiple-drivers 
cxxrtl: don't assert on wires with multiple drivers
 2020-11-01 13:52:59 +00:00
whitequark cdf4ce9871 cxxrtl: don't assert on wires with multiple drivers. 
Fixes #2374.
 2020-11-01 12:49:30 +00:00
Yosys Bot 56054f2ce3 Bump version 2020-11-01 00:10:05 +00:00
whitequark dfeff65c2b
Merge pull request #2416 from QuantamHD/master 
Adds support for defining abc location at runtime
 2020-10-31 07:59:44 +00:00
Yosys Bot 166a84bdb8 Bump version 2020-10-31 00:10:15 +00:00
Miodrag Milanovic c228cb74d6 Update verific version 2020-10-30 08:32:59 +01:00
Xiretza 86e0440da9
Update nexus arch tests to new harness 2020-10-29 14:42:07 +01:00
Ethan Mahintorabi 5c36e7757c This patch adds support for defining the ABC location at runtime instead of at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase. 
This change should be backwards compatible with the existing behavior.
 2020-10-28 19:00:06 -07:00
Yosys Bot e2a39bb1e7 Bump version 2020-10-25 00:10:05 +00:00
Marcelina Kościelnicka d3b6b7fe98 xilinx: Fix attributes_test.ys 
This test pretty much passes by accident — the `prep` command runs
memory_collect without memory_dff first, which prevents merging read
register into the memory, and thus blocks block RAM inference for a
reason completely unrelated to the attribute.

The attribute setting didn't actually work because it was set on the
containing module instead of the actual memory.
 2020-10-24 23:52:37 +02:00
Yosys Bot 623526d17d Bump version 2020-10-23 00:10:07 +00:00
David Shah 6d63e58e46 nexus: Add make_transp to BRAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-22 15:11:59 +01:00
N. Engelhardt 3b86b5da5f
Merge pull request #2403 from nakengelhardt/sim_timescale 
sim -vcd: add date, version, and option for timescale
 2020-10-22 14:01:24 +02:00
Marcelina Kościelnicka eb76d35e80 memory_dff: Fix needlessly duplicating enable bits. 
When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow.  Fix this by adding a simple cache.

Fixes #2409.
 2020-10-22 13:03:42 +02:00
Yosys Bot 1a7a597e07 Bump version 2020-10-22 00:10:06 +00:00
Marcelina Kościelnicka 2d340cd355 btor: Use Mem helper. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka f272c8b407 smt2: Use Mem helper. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka ec483b7c3b verilog_backend: Use Mem helper. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka b065e09045 sim: Use Mem helper. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka e759e301a8 clk2fflogic: Use Mem helper. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 06141db233 opt_mem: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 21896e2a02 memory_bram: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 1e8098279f memory_map: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka d390b380e1 memory_unpack: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka e9978aaf15 memory_collect: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 248b193d6d memory_nordff: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 8720482ebd Add new helper structures to represent memories. 2020-10-21 17:51:20 +02:00
N. Engelhardt 1c96a0b1d5 use strftime instead of put_time for gcc 4.8 compatibility 2020-10-21 17:47:00 +02:00
Yosys Bot c76d533e07 Bump version 2020-10-21 00:10:07 +00:00
clairexen e919d0c125
Merge pull request #2405 from byuccl/fix_xilinx_cells 
xilinx/cells_sim.v: Move signal declaration to before first use
 2020-10-20 17:11:36 +02:00
clairexen 099d0c2a8a
Merge pull request #2404 from YosysHQ/claire/fixrpcargs 
Fix argument handling in connect_rpc
 2020-10-20 11:32:35 +02:00
Yosys Bot 06347b119b Bump version 2020-10-20 00:10:06 +00:00
Jeff Goeders 8be56960a2 Move signal declarations to before first use 
Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
 2020-10-19 16:09:18 -06:00