riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,039 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

4148 Commits

Author SHA1 Message Date
George Rennie 58af70624f opt_demorgan: skip zero width cells 2024-09-24 14:24:59 +01:00
N. Engelhardt 8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail 2024-09-23 15:19:48 +02:00
Martin Povišer 38de01807e Mark `bufnorm` experimental 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 8bb70bac8d Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d027ead4b5 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf f4b7ea5fb3 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 32808a0393 Improvements and fixes to "bufnorm" cmd 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d0b5dfa6ef Add bufnorm pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Emil J 52382c6544
Merge pull request #4583 from YosysHQ/emil/clock_gate 
clockgate: centralize clock enables out of FFs
 2024-09-16 15:41:01 +02:00
Emil J. Tywoniak f193bcf683 clockgate: help string 2024-09-16 14:20:33 +02:00
Emil J. Tywoniak be7c93ec6d clockgate: 1-bit const 0 2024-09-16 13:58:27 +02:00
Emil J a8a92d3469
clockgate: help string 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-09-16 13:55:53 +02:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Emil J. Tywoniak 1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00
Martin Povišer 34572708d5
Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode 
internal_stats: astnode (sizeof)
 2024-09-11 12:21:29 +02:00
Emil J. Tywoniak 1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Emil J. Tywoniak 8b464341c2 clockgate: no initvals 2024-09-11 10:24:48 +02:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Emil J. Tywoniak 7e473299bd clockgate: bail on constant signals 2024-09-09 21:20:19 +02:00
Emil J. Tywoniak e64fceef70 clockgate: prototype clock gating 2024-09-09 15:00:54 +02:00
Hoa Nguyen c1205ebc42 Initialize area stats in stat pass 
Currently, the area variables in the stat struct are not initialized.
This caused the area stats occasionally being an erroneous value.

Signed-off-by: Hoa Nguyen <hnpl@google.com>
 2024-09-07 21:30:58 -07:00
Miodrag Milanović b20df72e1e
Merge pull request #4536 from YosysHQ/functional 
Functional Backend
 2024-09-06 10:05:04 +02:00
Emil J. Tywoniak 14b9155492 internal_stats: fix doc build by adding a help string 2024-09-05 11:22:21 +02:00
Martin Povišer 68fbca8769
Merge pull request #4554 from YosysHQ/emil/devstat 
internal_stats: init, report current memory consumption on linux and mac
 2024-09-03 21:06:46 +02:00
Emil J. Tywoniak 0ce7631956 internal_stats: init, report current memory consumption on linux and mac 2024-09-03 19:28:24 +02:00
George Rennie bdb5d45591 proc_dff: respect sync rule priorities when generating complex dffsrs 
* This fixes #4560, where previously the order that sync rules were
  processed in depended on the order they were pulled out of a std::map.
  This PR changes this to process them in the order they are found in,
  respecting the priorities among the async signals
 2024-08-28 15:48:07 +01:00
N. Engelhardt 0fc5812dcd
Merge pull request #4541 from YosysHQ/krys/compiler-warnings 
Resolve (some) compiler warnings
 2024-08-26 15:04:16 +02:00
Emily Schmidt 850b3a6c29 convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h 2024-08-21 11:04:08 +01:00
Emily Schmidt 8c0f625c3a functional backend: topological sort starts with the output and next states nodes, other nodes get deleted 2024-08-21 11:03:29 +01:00
Emily Schmidt bdb59ffc8e add -fst-noinit flag to sim for not initializing the state from the fst file 2024-08-21 11:03:29 +01:00
Emily Schmidt dd5ec84a26 fix bugs in drivertools 2024-08-21 11:01:09 +01:00
Jannis Harder d4e3daa9d0 ComputeGraph datatype for the upcoming functional backend 2024-08-21 11:01:09 +01:00
Jannis Harder 68c3a47945 WIP temporary drivertools example 2024-08-21 11:01:08 +01:00
Emil J e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix 
peepopt: avoid shift-amount underflow
 2024-08-19 15:45:46 +02:00
Krystine Sherwin 7b47f645d7
Address warnings 
- Setting default values
- Fixing mismatched types
- Guarding unused var
 2024-08-16 04:30:31 +12:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Martin Povišer 78382eaa6f libparse: Adjust whitespace 2024-08-13 18:47:36 +02:00
Martin Povišer 4c3203866f exec: Add missing newline 2024-08-07 13:02:00 +02:00
Miodrag Milanovic 6d98418f3d Set ranges on exported wires in VCD and FST 2024-08-02 15:23:00 +02:00
Emil J 92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy 
cost: add keep_hierarchy pass with min_cost argument
 2024-07-29 16:33:08 +02:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
Emil J. Tywoniak 4b29f64142 cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter 2024-07-29 10:26:02 +02:00
N. Engelhardt dd3637f9f0
Merge pull request #4506 from povik/synthprop-formatting 
synthprop: Reformat the help
 2024-07-26 12:28:09 +02:00
Martin Povišer 7ee685a0b0 proc_rom: Set `src` on the emitted memory 2024-07-25 23:14:27 +01:00
Martin Povišer e063b96104 synthprop: Reformat the help 2024-07-25 11:43:58 +02:00
Martin Povišer 0cefe8a1e8 check: Skip detailed edge modeling if costly 2024-07-18 13:08:19 +02:00
Martin Povišer e70b1251ad check: Adjust prints 2024-07-18 13:08:19 +02:00
Martin Povišer 3f71bc469d check: Rephrase comment 2024-07-18 13:08:19 +02:00
Emil J 1166238c0f
Merge pull request #4176 from povik/opt_expr-performance 
Improve `opt_expr` performance
 2024-07-15 16:10:25 +02:00