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311 Commits

Author SHA1 Message Date
Zachary Snow 8206546c45 Fix constants bound to single bit arguments (fixes #2383) 2020-12-22 17:01:03 -07:00
whitequark 3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint 
Allow constant function calls in constant function arguments
 2020-12-22 01:31:25 +00:00
Zachary Snow 0d8e5d965f Sign extend port connections where necessary 
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
 2020-12-18 20:33:14 -07:00
Zachary Snow 186d6df4c3 Allow constant function calls in constant function arguments 2020-12-07 13:53:27 -07:00
Claire Xen cf67e6a397
Merge pull request #2133 from dh73/nodev_head 
Adding latch tests for shift&mask AST dynamic part-select enhancements
 2020-11-25 09:44:23 +01:00
Xiretza acd47bbd52
tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
clairexen a10893072b
Merge pull request #2352 from zachjs/const-func-localparam 
Allow localparams in constant functions
 2020-09-01 17:31:48 +02:00
Zachary Snow ecc5c23b4d Fix constant args used with function ports split across declarations 2020-08-29 13:31:02 -04:00
Zachary Snow 74abc3bbfd Allow localparams in constant functions 2020-08-20 20:10:24 -04:00
clairexen 6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup 
Remove passes redundant with opt_dff
 2020-08-20 16:21:58 +02:00
Claire Wolf 7f767bf2b7 Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-08-18 17:29:49 +02:00
clairexen 5ee9349647
Merge pull request #2281 from zachjs/const-real 
Allow reals as constant function parameters
 2020-08-18 17:22:20 +02:00
Marcelina Kościelnicka a0e99a9f3f peepopt: Remove now-redundant dffmux pattern. 2020-08-07 13:21:34 +02:00
clairexen 66afed6f55
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef 
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
 2020-07-28 12:56:22 +02:00
Marcelina Kościelnicka a1a0abf52a equiv_induct: Fix up assumption for $equiv cells in -undef mode. 
Before this fix, equiv_induct only assumed that one of the following is
true:

- defined value of A is equal to defined value of B
- A is undefined

This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A.  Instead, tighten this up to OR of the following:

- defined value of A is equal to defined value of B, and B is not
  undefined
- A is undefined
 2020-07-27 18:36:13 +02:00
Zachary Snow f69daf4830 Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
Zachary Snow 59c4ad8ed3 Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
Zachary Snow f285f7b769 Allow reals as constant function parameters 2020-07-19 20:27:09 -06:00
Kamil Rakoczy de649b9194 Revert "Revert PRs #2203 and #2244." 
This reverts commit 9c120b89ac.
 2020-07-10 09:59:48 +02:00
whitequark 9c120b89ac Revert PRs #2203 and #2244. 
This reverts commit 7e83a51fc9.
This reverts commit b422f2e4d0.
This reverts commit 7cb56f34b0.
This reverts commit 6f9be939bd.
This reverts commit 76a34dc5f3.
 2020-07-09 19:36:32 +00:00
Kamil Rakoczy b422f2e4d0 Add logic param and integer bad syntax tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-06 09:18:48 +02:00
clairexen 7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar 
Signed and macro grammar update
 2020-07-01 16:41:32 +02:00
Zachary Snow 27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Kamil Rakoczy 76a34dc5f3 Add signed/unsigned tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:38:20 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
diego d68a8f9e2b Removing trailing whitespace 2020-06-10 10:35:40 -05:00
diego 3c2a1171ff Adding latch tests for shift&mask AST dynamic part-select enhancements 2020-06-09 15:17:01 -05:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
Eddie Hung 46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 
tests: reduce test warnings
 2020-06-03 08:37:07 -07:00
Eddie Hung d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
Alberto Gonzalez 6228b10c9f
printattrs: Add test. 2020-05-27 08:00:00 +00:00
Eddie Hung 60aa804915 tests: fix some test warnings 2020-05-25 10:07:58 -07:00
Eddie Hung 33b03ce904 xaiger: add testcase 2020-05-24 08:48:23 -07:00
Eddie Hung 13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung 48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung a299e606f8
Merge pull request #2028 from zachjs/master 
verilog: allow null gen-if then block
 2020-05-06 12:10:28 -07:00
Zachary Snow 8f9bba1bbf verilog: allow null gen-if then block 2020-05-06 08:43:02 -04:00
Eddie Hung 7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00
Eddie Hung eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung ad8e7878f6 tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
Eddie Hung db13852ed6 test: add test for #2014 2020-05-02 14:22:37 -07:00
Eddie Hung db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966 
tests: fix various/plugin.sh when PREFIX != /usr/local/share
 2020-04-22 10:19:30 -07:00
Eddie Hung 28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import 
design: -import to not count black/white-boxes as candidates for top
 2020-04-22 09:32:13 -07:00
Eddie Hung 634b5e2d9f tests: use `yosys-config --datdir` instead of hard-coded 2020-04-22 08:29:45 -07:00
Claire Wolf c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const 
sim: Fix handling of constant-connected cell inputs at startup
 2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka 846c79b312 hierarchy: Convert positional parameters to named. 
Fixes #1821.
 2020-04-21 19:09:00 +02:00
Claire Wolf 9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite 
Improved rewrite code for writing to bit slice
 2020-04-21 18:46:52 +02:00
David Shah abf81c7639 sim: Fix handling of constant-connected cell inputs at startup 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-21 08:58:52 +01:00
Eddie Hung caf4071c8b Remove '-ignore_unknown_cells' option from 'sat' 2020-04-20 11:58:23 -07:00
Eddie Hung a1573058e9 Simplify test case script 2020-04-20 11:54:10 -07:00
diego 22f440506b Modifications of tests as per Eddie's request 2020-04-20 12:45:35 -05:00
Eddie Hung 34d8ff8b56 abc9: add testcase reduced from #1970 2020-04-20 09:38:29 -07:00
Eddie Hung 9eace8f360 design: add test 2020-04-16 12:48:40 -07:00
Eddie Hung e8a841467f tests: add design -delete tests 2020-04-16 08:05:18 -07:00
David Shah 4d02505820 ast: Fix handling of identifiers in the global scope 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-16 10:30:07 +01:00
Eddie Hung e7121cc15c tests: add testcases from #1876 2020-04-14 12:39:10 -07:00
Eddie Hung f11dd6e208 tests: add a quick plugin test 2020-04-09 09:45:20 -07:00
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
David Shah fa77fb857b Add test for abc9+mince issue 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-20 20:35:28 +00:00
Marcin Kościelnicki e91368a5f4 fsm_extract: Initialize celltypes with full design. 
Fixes #1781.
 2020-03-19 18:51:21 +01:00
Alberto Gonzalez a09b260c01
Add test for `exec` command. 2020-03-16 07:52:58 +00:00
Miodrag Milanović 569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux 
refixed parsing of constant with comment between size and value
 2020-03-14 13:34:59 +02:00
Marcus Comstedt dd562f29e7 Add regression tests for new handling of comments in constants 2020-03-14 11:41:09 +01:00
Miodrag Milanović faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations 
Set AST node source location in more parser rules.
 2020-03-14 11:18:39 +02:00
Miodrag Milanovic 5b73e7c63a Added back tests for logger 2020-03-13 15:00:18 +01:00
Eddie Hung 3ada82639f verilog: add test 2020-03-11 06:51:03 -07:00
David Shah ddcd87b577
Merge pull request #1721 from YosysHQ/dave/tribuf-unused 
deminout: Don't demote inouts with unused bits
 2020-03-10 13:51:40 +00:00
David Shah 5cae9c6e16 deminout: Don't demote inouts with unused bits 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-04 18:44:38 +00:00
Claire Wolf b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Claire Wolf 879124333f
Merge pull request #1519 from YosysHQ/eddie/submod_po 
submod: several bugfixes
 2020-03-03 08:19:06 -08:00
Eddie Hung 4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify 
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
 2020-03-02 12:32:27 -08:00
Eddie Hung 5bba9c3640 ast: fixes #1710; do not generate RTLIL for unreachable ternary 2020-02-27 16:55:55 -08:00
Eddie Hung f858219c4e Cleanup tests 2020-02-27 10:17:29 -08:00
Alberto Gonzalez 2c2f092c90
Change attribute search value to specify precise location instead of simple line number. 2020-02-24 01:39:36 +00:00
Eddie Hung 1d401a7991 clean: ignore specify-s inside cells when determining whether to keep 2020-02-19 10:45:10 -08:00
Eddie Hung d20c1dac73 verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
Eddie Hung 6b58c1820c verilog: improve specify support when not in -specify mode 2020-02-13 13:27:15 -08:00
Eddie Hung 2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung 7cfdf4ffa7 verilog: fix $specify3 check 2020-02-13 12:42:04 -08:00
N. Engelhardt e069259a53
Merge pull request #1679 from thasti/delay-parsing 
Fix crash on wire declaration with delay
 2020-02-13 12:01:27 +01:00
Stefan Biereigel 90c78f1f85 add testcase for #1614 2020-02-03 21:29:54 +01:00
David Shah ebe1d7d5ab sv: More tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 7e741714df hierarchy: Correct handling of wildcard port connections with default values 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah a210675d71 sv: Add tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf 
ast: Add support for $sformatf system function
 2020-02-02 14:53:46 +00:00
Eddie Hung 136842b1ef Merge branch 'master' into eddie/submod_po 2020-02-01 02:14:19 -08:00
Eddie Hung d004953772 Add "help -all" and "help -celltypes" sanity test 2020-01-28 18:11:34 -08:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung cd8f55a911 write_xaiger: fix for (* keep *) on flop output 2020-01-21 09:43:04 -08:00
David Shah 22c967e35e ast: Add support for $sformatf system function 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-19 21:20:17 +00:00
Eddie Hung 6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung 00964e999d autoname: add testcase with $-prefix-ed port 2020-01-14 10:13:03 -08:00
Eddie Hung fc4b8b8991 Remove submod changes 2019-12-30 14:56:14 -08:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531 
verilog: preserve size of $genval$-s in for loops
 2019-12-19 12:21:33 -05:00
N. Engelhardt abcd82daca add assert option to scratchpad command 2019-12-16 14:00:21 +01:00
N. Engelhardt 1187e91c2f add test and make help message more verbose 2019-12-12 20:51:59 +01:00