Clifford Wolf
12440fcc8f
Add $lut support to Verilog back-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-06 00:18:01 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
d9a2b43014
Add $dlatch support to write_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-22 16:03:26 +02:00
Clifford Wolf
adf1754729
Add $shiftx support to verilog front-end
2017-10-07 13:40:54 +02:00
Clifford Wolf
65f91e5120
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
2017-10-03 17:31:21 +02:00
dh73
e480847753
Fixed wrong declaration in Verilog backend
2017-10-01 11:11:32 -05:00
dh73
cbaba62401
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
ce132cf652
Cleanups and fixed in write_verilog regarding reg init
2016-11-16 12:00:39 +01:00
Clifford Wolf
3db2ac4e00
Added hex constant support to write_verilog
2016-11-03 12:13:23 +01:00
Clifford Wolf
caa2fc62ef
Adde "write_verilog -renameprefix -v"
2016-11-01 11:30:27 +01:00
Clifford Wolf
75bf7416f0
Bugfix in partial mem write handling in verilog back-end
2016-08-20 13:06:06 +02:00
Clifford Wolf
9b8e06bee1
Added missing support for mem read enable ports to verilog back-end
2016-08-18 21:47:02 +02:00
Clifford Wolf
f0a8713fea
Fixed upto handling in verilog back-end
2016-08-15 08:26:20 +02:00
Clifford Wolf
5fe13a16ea
Added "write_verilog -defparam"
2016-07-30 12:46:06 +02:00
Clifford Wolf
7fa61cba1b
Added "write_verilog -nodec -nostr"
2016-07-30 12:38:40 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
2a8d5e64f5
Bugfix in write_verilog for RTLIL processes
2016-03-14 13:03:28 +01:00
Clifford Wolf
4ac202e2a5
Bugfixes in writing of memories as Verilog
2015-09-25 13:49:26 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
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Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
0350074819
Re-created command-reference-manual.tex, copied some doc fixes to online help
2015-08-14 11:27:19 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
luke whittlesey
2f90499e3d
$mem cell in verilog backend : grouped writes by clock
2015-06-08 17:35:40 -04:00
luke whittlesey
a8fe040906
Bug fix in $mem verilog backend + changed tests/bram flow of make test.
2015-06-04 16:12:40 -04:00
Clifford Wolf
4744bb95fb
Some fixes for $mem in verilog back-end
2015-05-20 13:55:50 +02:00
Clifford Wolf
42348cddd9
Merge pull request #63 from wluker/verilog-backend-mem
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Fixed bug in $mem cell verilog code generation.
2015-05-11 21:38:06 +02:00
luke whittlesey
3bb5f064b8
Fixed bug in $mem cell verilog code generation.
2015-05-11 14:05:18 -04:00
Clifford Wolf
9e56739634
Disabled broken $mem support in verilog backend
2015-05-10 21:38:41 +02:00
luke whittlesey
6de8fea2c7
Made changes recommended by Clifford Wolf ...
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Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
2015-05-10 11:33:24 -04:00
luke whittlesey
2c1e150297
Verilog backend for $mem cells should now be able to handle different
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write-enable bits and RD_TRANSPARENT parameter settings.
2015-05-08 15:29:51 -04:00
luke whittlesey
c0b68f4848
Added support for $mem cells in the verilog backend.
2015-05-07 13:03:09 -04:00
Clifford Wolf
d176e613c2
Minor fixes in handling of "init" attribute
2015-04-09 15:12:26 +02:00
Clifford Wolf
b0c0ede879
Added "init" attribute support to verilog backend
2015-04-04 18:06:52 +02:00
Clifford Wolf
67e6dcd34a
Added Verilog backend $dffsr support
2015-03-18 08:01:37 +01:00
Clifford Wolf
756b4064b2
Fixed "write_verilog -attr2comment" handling of "*/" in strings
2015-02-13 22:48:10 +01:00
Clifford Wolf
43951099cf
Added dict/pool.sort()
2015-01-24 00:13:27 +01:00
Clifford Wolf
146f769bee
Cosmetic changes in verilog output format
2015-01-02 22:57:08 +01:00
Clifford Wolf
9e6fb0b02c
Replaced std::unordered_map as implementation for Yosys::dict
2014-12-26 21:35:22 +01:00
Clifford Wolf
a6c96b986b
Added Yosys::{dict,nodict,vector} container types
2014-12-26 10:53:21 +01:00
Clifford Wolf
5df192e71c
Added $dffe support to write_verilog
2014-12-20 00:03:20 +01:00
Clifford Wolf
461594bb83
Fixed generation of temp names in verilog backend
2014-11-07 14:40:06 +01:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
9329a76818
Various bug fixes (related to $macc model testing)
2014-09-06 20:30:46 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
b9cb483f3e
Using $pos models for $bu0
2014-09-03 21:20:59 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
f82c978e08
Fixed AOI/OAI expr handling in verilog backend
2014-08-16 22:05:09 +02:00
Clifford Wolf
47c2637a96
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
746aac540b
Refactoring of CellType class
2014-08-14 15:46:51 +02:00
Clifford Wolf
88cf00ce78
Be more conservative with printing decimal numbers in verilog backend
2014-08-02 21:54:02 +02:00
Clifford Wolf
ca1b5d50e0
Improved verilog output for ordinary $mux cells
2014-08-02 21:10:08 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
27a872d1e7
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
97a59851a6
Added RTLIL::Cell::has(portname)
2014-07-26 16:11:28 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
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git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
5826670009
Various RTLIL::SigSpec related code cleanups
2014-07-25 14:25:42 +02:00
Clifford Wolf
c094c53de8
Removed RTLIL::SigSpec::optimize()
2014-07-23 20:32:28 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
a30e2857c7
Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend
2014-07-20 02:16:30 +02:00
Clifford Wolf
0c67393313
Added support for $bu0 to verilog backend
2014-07-20 01:56:16 +02:00
Clifford Wolf
fc3b3c4ec3
Added $slice and $concat cell types
2014-02-07 17:44:57 +01:00
Clifford Wolf
369bf81a70
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
Clifford Wolf
f4b46ed31e
Replaced signed_parameters API with CONST_FLAG_SIGNED
2013-12-04 14:24:44 +01:00
Clifford Wolf
93a70959f3
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
Clifford Wolf
41205afc39
Added proper dumping of signed/unsigned parameters to verilog backend
2013-11-24 17:47:22 +01:00
Clifford Wolf
295e352ba6
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
Clifford Wolf
40d9542647
Implemented $_DFFSR_ expression generator in verilog backend
2013-11-21 21:52:30 +01:00
Clifford Wolf
1dcb683fcb
Write yosys version to output files
2013-11-03 21:41:39 +01:00
Clifford Wolf
e9dede01ca
Fixed handling of boolean attributes (backends)
2013-10-24 11:27:30 +02:00
Clifford Wolf
eae43e2db4
Fixed handling of boolean attributes (kernel)
2013-10-24 10:59:27 +02:00
Clifford Wolf
e0f693cbb0
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00
Clifford Wolf
5998c101a4
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
Clifford Wolf
73914d1a41
Added -selected option to various backends
2013-09-03 19:10:11 +02:00
Clifford Wolf
39ee561169
More explicit integer output in verilog backend
2013-08-22 20:31:04 +02:00
Clifford Wolf
7bfc7b61a8
Implemented proper handling of stub placeholder modules
2013-03-28 09:20:10 +01:00
Clifford Wolf
87c7717566
Avoid verilog-2k in verilog backend
2013-03-21 09:51:25 +01:00
Clifford Wolf
11789db206
More support code for $sr cells
2013-03-14 11:15:00 +01:00
Clifford Wolf
441e5fbfca
Fixed a gcc compiler warning [-Wparentheses]
2013-03-03 22:45:06 +01:00
Clifford Wolf
7fccad92f7
Added more help messages
2013-03-01 00:36:19 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00