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8791 Commits

Author SHA1 Message Date
Claire Wolf 5c2508cef8 Improve logging use of experimental features 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-28 17:51:50 +01:00
Claire Wolf 4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning 
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
 2020-01-28 17:40:28 +01:00
N. Engelhardt 086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
David Shah 6fd9cae5ca opt_reduce: Call check() per run rather than per optimised cell 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-28 09:42:01 +00:00
Pepijn de Vos 409e532433 redirect fuser stderr to /dev/null 2020-01-28 10:02:41 +01:00
Claire Wolf 8f40113826
Merge pull request #1553 from whitequark/manual-dffx 
Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells
 2020-01-28 09:41:08 +01:00
Eddie Hung 21ce1b37fb abc9_ops: -check for negative arrival/required times 2020-01-27 14:22:46 -08:00
Eddie Hung e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 
Just like Verilog...
 2020-01-27 14:02:13 -08:00
Eddie Hung cfb0366a18 Import tests from #1628 2020-01-27 13:56:16 -08:00
Eddie Hung ce6a690d27 xilinx/ice40/ecp5: undo permuting LUT masks in lut_map 
Now done in read_aiger
 2020-01-27 13:30:27 -08:00
Eddie Hung 48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung e0bdf5d7a9 Fix typo 2020-01-27 12:30:39 -08:00
Eddie Hung f2576c096c Merge branch 'eddie/abc9_refactor' into eddie/abc9_required 2020-01-27 12:29:28 -08:00
Eddie Hung 9009b76a69 abc9_ops: add comments 2020-01-27 11:18:21 -08:00
Eddie Hung f443695a38 Merge remote-tracking branch 'origin/master' into eddie/verific_help 2020-01-27 10:34:10 -08:00
Eddie Hung d730bba6d2 verific: no help() when no YOSYS_ENABLE_VERIFIC 2020-01-27 10:32:18 -08:00
Eddie Hung 7b445121cc verific: also unflatten for 'hierarchy' flow as per @cliffordwolf 2020-01-27 10:15:22 -08:00
Eddie Hung af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings 
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
 2020-01-27 09:54:04 -08:00
Claire Wolf cef607c8b7 Add log_experimental() and experimental() API and "yosys -x" 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-27 18:27:47 +01:00
Claire Wolf 07a12ebd4f
Merge pull request #1658 from YosysHQ/clifford/smtbmcsolvernotfound 
Improve yosys-smtbmc "solver not found" handling
 2020-01-27 17:59:58 +01:00
Claire Wolf 485f31f681 Improve yosys-smtbmc "solver not found" handling 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-27 17:48:56 +01:00
Claire Wolf de6006fbc8
Merge pull request #1613 from porglezomp-misc/version-flag-alias 
Add --version and -version as aliases for -V
 2020-01-27 12:59:27 +01:00
Eddie Hung c7fbe13db5 read_aiger: set abc9_box_seq attr 2020-01-24 13:11:43 -08:00
Eddie Hung 81e6b040a4 ice40: add SB_SPRAM256KA arrival time 2020-01-24 12:17:09 -08:00
Eddie Hung b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung cccc0ae112 verific: unflatten struct ports 2020-01-24 10:12:52 -08:00
Eddie Hung dbf351390e abc9: -reintegrate recover type from existing cell, check against boxid 2020-01-23 22:45:34 -08:00
Eddie Hung 2d795fb8c0 simple_abc9 tests to discard whitebox before write for sim 2020-01-23 22:07:43 -08:00
Eddie Hung dca1c806ec simple_abc9 tests to discard whitebox before write for sim 2020-01-23 19:55:11 -08:00
Eddie Hung e471b330ac abc_box_id -> abc9_box_id in test 2020-01-23 19:12:19 -08:00
Eddie Hung 245873d42d abc9: warning message if no modules selected 2020-01-23 19:08:51 -08:00
Eddie Hung 7858cf20a9 Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-23 19:02:27 -08:00
Eddie Hung 11e50c0e9e Test for (* keep *)-ed abc9_box_id 2020-01-23 18:56:25 -08:00
Eddie Hung f180dba753 abc9_ops: -prep_xaiger to skip (* keep *) cells 2020-01-23 18:56:06 -08:00
Eddie Hung 48aec34e0d abc_box_id -> abc9_box_id in test 2020-01-23 18:53:14 -08:00
Eddie Hung 1d4314d888 abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_* 2020-01-23 14:58:56 -08:00
Eddie Hung af0e7637a2 alumacc: undo accidental commit 2020-01-22 20:54:03 -08:00
Eddie Hung da134701cd Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-22 14:22:03 -08:00
Eddie Hung 73526a6f10 read_aiger: also parse abc9_mergeability 2020-01-22 14:21:25 -08:00
Eddie Hung 8eb5bb258c Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor 2020-01-22 12:30:14 -08:00
Eddie Hung da6abc0149
Merge pull request #1652 from YosysHQ/eddie/abc9_fixes 
Eddie/abc9 fixes
 2020-01-22 12:27:41 -08:00
Eddie Hung a94b41011d abc9: error out if flip-flop init is 1'b1 for '-dff' 
Due to ABC sequential synthesis restriction
 2020-01-22 10:08:48 -08:00
Eddie Hung 3b44b53e94 abc9: fix scratchpad entry abc9.verify 2020-01-22 09:36:54 -08:00
Eddie Hung 5aaa19f1ab Update tests with reduced area 2020-01-21 16:50:04 -08:00
Eddie Hung 72e4540ca9 Explicitly create separate $mux cells 2020-01-21 16:49:34 -08:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung 152dfd3dd4 Fix tests -- when Y_WIDTH is non-pow-2 2020-01-21 15:19:41 -08:00
Eddie Hung 8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung 7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung cd093c00f8 read_aiger: discard LUT inputs with nodeID == 0; not < 2 2020-01-21 11:56:30 -08:00