7 Commits

Author	SHA1	Message	Date
Clifford Wolf	8b508dc90b	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	2014-02-21 23:34:45 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	64a5f8f75e	Added "proc_arst -global_arst" feature	2013-11-20 21:00:43 +01:00
Clifford Wolf	56ea230676	Added handling of multiple async paths in proc_arst	2013-10-19 00:50:13 +02:00
Clifford Wolf	227520f94d	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
Clifford Wolf	f952309c81	Added help messages to proc_* passes	2013-03-01 09:26:29 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00