Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
...
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Alberto Gonzalez
d6de14a0d6
Use more descriptive variable name.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-06 14:37:07 +00:00
Alberto Gonzalez
5431ce694c
Clean up `passes/hierarchy/submod.cc`.
2020-04-05 04:39:54 +00:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Eddie Hung
a265a84632
Use pool instead of std::set for determinism
2019-12-02 01:28:28 -08:00
Eddie Hung
b3a66dff7c
Move \init signal for non-port signals as long as internally driven
2019-11-28 12:57:36 -08:00
Eddie Hung
130d3b9639
Fix multiple driver issue
2019-11-27 13:23:31 -08:00
Eddie Hung
1c0ee4f786
Do not replace constants with same wire
2019-11-27 08:18:41 -08:00
Eddie Hung
c7aa2c6b79
Cleanup
2019-11-27 01:01:24 -08:00
Eddie Hung
cb05fe0f70
Check for nullptr
2019-11-27 00:51:39 -08:00
Eddie Hung
d960feeeb0
Stray log_dump
2019-11-27 00:50:25 -08:00
Eddie Hung
8c813632b6
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
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This reverts commit cba3073026
.
2019-11-27 00:48:22 -08:00
Eddie Hung
969f511415
Promote output wires in sigmap so that can be detected
2019-11-26 23:39:14 -08:00
Eddie Hung
5e487b103c
Fix submod -hidden
2019-11-26 23:26:25 -08:00
Eddie Hung
435d33c373
Add -hidden option to submod
2019-11-26 23:26:12 -08:00
Eddie Hung
eb666b4677
Update docs with bullet points
2019-11-26 11:12:58 -08:00
Eddie Hung
0d7ba77426
Move \init from source wire to submod if output port
2019-11-25 16:07:47 -08:00
Eddie Hung
cba3073026
submod to bitty rather bussy, for bussy wires used as input and output
2019-11-22 20:53:58 -08:00
Eddie Hung
8119383f81
Constant driven signals are also an input to submodules
2019-11-22 17:23:51 -08:00
Eddie Hung
573396851a
Oops
2019-11-22 17:03:30 -08:00
Eddie Hung
6a52897aee
sigmap(wire) should inherit port_output status of POs
2019-11-22 16:48:11 -08:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
1827a48964
Minor bugfix in submod
2016-11-09 13:13:26 +01:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
d00c63c927
Added "submod -copy"
2016-01-08 09:08:12 +01:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
946ddff9ce
Changed a lot of code to the new RTLIL::Wire constructors
2014-07-26 20:12:50 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
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git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
4755e14e7b
Added copy-constructor-like module->addCell(name, other) method
2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
4e802eb7f6
Fixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 15:36:09 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
8d04ca7d22
Added call_on_selection() and call_on_module() API
2014-07-20 15:33:06 +02:00
Clifford Wolf
6644f80d97
Moved some passes to other source directories
2014-02-08 14:39:15 +01:00