Eddie Hung
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18cabe9370
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Output has priority over input when stitching in abc9
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2019-08-29 17:24:03 -07:00 |
Eddie Hung
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c52db44f9a
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Group abc_* attribute doc with other attributes
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2019-08-29 12:13:52 -07:00 |
Eddie Hung
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3e0f73c3df
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abc9 to not call "clean" at end of run (often called outside)
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2019-08-29 12:12:59 -07:00 |
Sergey
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5dda8f39a6
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Merge pull request #2 from YosysHQ/master
Pull from upstream
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2019-08-29 21:09:40 +03:00 |
Sergey
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d360693040
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Merge pull request #3 from YosysHQ/Sergey/tests_ice40
Merge my changes to tests_ice40 branch
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2019-08-29 21:07:34 +03:00 |
Eddie Hung
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1467761060
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Fix typo that's gone unnoticed for 5 months!?!
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2019-08-29 10:33:28 -07:00 |
Eddie Hung
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67587bad7f
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Add constant expression attribute to test
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2019-08-29 09:10:20 -07:00 |
Eddie Hung
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83ffec26cb
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Remove newline
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2019-08-29 09:08:58 -07:00 |
Eddie Hung
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6510297712
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Restore non-deferred code, deferred case to ignore non constant attr
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2019-08-29 09:02:10 -07:00 |
Eddie Hung
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25b1670a84
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Rename boxes too
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2019-08-29 07:03:32 -07:00 |
Clifford Wolf
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89695fd3ab
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Bump YOSYS_VER
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-29 12:05:26 +02:00 |
SergeyDegtyar
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d588c6898f
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Add comments for examples from Lattice user guide
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2019-08-29 10:49:46 +03:00 |
Eddie Hung
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116c249601
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-auto-top should check $abstract (deferred) modules with (* top *)
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2019-08-28 19:59:25 -07:00 |
Eddie Hung
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34ae29295d
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read_verilog -defer should still populate module attributes
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2019-08-28 19:59:09 -07:00 |
Eddie Hung
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1fdb3fc98c
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Add failing test
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2019-08-28 19:58:58 -07:00 |
Eddie Hung
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13ecd8b0df
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Add run-test.sh too
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2019-08-28 18:47:48 -07:00 |
Eddie Hung
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a4f641f230
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Do not overwrite LUT param
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2019-08-28 18:46:53 -07:00 |
Eddie Hung
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e301a3dadb
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Add SB_CARRY to ice40_opt test
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2019-08-28 18:46:53 -07:00 |
Eddie Hung
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dd42aa87b9
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Add ice40_opt test
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2019-08-28 18:46:53 -07:00 |
Eddie Hung
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4eb5847dbd
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Cleanup
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2019-08-28 18:10:33 -07:00 |
Eddie Hung
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d46d38e4d5
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Trailing comma
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2019-08-28 17:25:54 -07:00 |
Eddie Hung
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f5b4bc847c
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Adapt to $__ICE40_CARRY_WRAPPER
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2019-08-28 17:25:05 -07:00 |
Eddie Hung
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e569f13870
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Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"
This reverts commit 2aedee1f0e .
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2019-08-28 17:22:44 -07:00 |
Eddie Hung
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2aedee1f0e
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Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with
CARRY_WRAPPER in the same way since I0 and I3 could be used
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2019-08-28 17:07:36 -07:00 |
Eddie Hung
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077e9d4ada
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Update box size and timings
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2019-08-28 17:07:24 -07:00 |
Eddie Hung
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129df7184a
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Update to new $__ICE40_CARRY_WRAPPER
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2019-08-28 17:07:07 -07:00 |
Eddie Hung
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0af64df10c
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Account for D port being a constant
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2019-08-28 15:32:38 -07:00 |
Eddie Hung
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b8a9f73089
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Comment out *.sh used for testbenches as we have no more
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2019-08-28 12:36:20 -07:00 |
Eddie Hung
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fc727fa5c9
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Merge pull request #1334 from YosysHQ/clifford/async2synclatch
Add $dlatch support to async2sync
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2019-08-28 12:36:06 -07:00 |
Eddie Hung
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87d5d9b8c8
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Use equiv for memory and dpram
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2019-08-28 12:30:35 -07:00 |
Eddie Hung
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ebd0a1875b
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Use equiv_opt for latches
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2019-08-28 12:21:15 -07:00 |
Eddie Hung
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32eef26ee2
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Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40
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2019-08-28 12:18:32 -07:00 |
Eddie Hung
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52c4655de3
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No need to replace Q of slice since $shiftx is autoremove-d
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2019-08-28 11:06:11 -07:00 |
Eddie Hung
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9314a0a42e
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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
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2019-08-28 10:51:39 -07:00 |
Eddie Hung
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11e3eb1009
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More cleanup
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2019-08-28 10:19:35 -07:00 |
Eddie Hung
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86b538bd02
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More cleanup
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2019-08-28 10:11:09 -07:00 |
Eddie Hung
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c4d1bd988b
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Do not use default_params dict, hardcode default values, cleanup
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2019-08-28 10:06:40 -07:00 |
Eddie Hung
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64ea147236
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Add .gitignore
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2019-08-28 09:55:34 -07:00 |
Eddie Hung
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2f493fb465
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Use test_pmgen for xilinx_srl
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2019-08-28 09:55:09 -07:00 |
Eddie Hung
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c3e9627afe
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Always generate if no match
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2019-08-28 09:54:56 -07:00 |
Eddie Hung
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0ebe2c9831
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Rename test_pmgen arg xilinx_srl.{fixed,variable}
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2019-08-28 09:27:03 -07:00 |
Eddie Hung
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2e9e745efa
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Do not simplemap for variable test
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2019-08-28 09:26:08 -07:00 |
Eddie Hung
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975aaf190f
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Add xilinx_srl test
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2019-08-28 09:24:19 -07:00 |
Eddie Hung
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ba5d81c7f1
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
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2019-08-28 09:21:03 -07:00 |
David Shah
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13424352cc
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Merge pull request #1332 from YosysHQ/dave/ecp5gsr
ecp5: Add GSR and SGSR support
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2019-08-28 12:44:02 +01:00 |
Clifford Wolf
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c84fef92df
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Merge pull request #1335 from YosysHQ/clifford/paramap
Add "paramap" pass
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2019-08-28 10:35:47 +02:00 |
Clifford Wolf
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47ffbf554e
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Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 10:06:42 +02:00 |
Clifford Wolf
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0fda0e821c
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Add "paramap" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 10:03:27 +02:00 |
Clifford Wolf
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c499dc3e73
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Add $dlatch support to async2sync
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 09:45:22 +02:00 |
SergeyDegtyar
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fe58790f37
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Revert "Add tests for ecp5"
This reverts commit 2270ead09f .
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2019-08-28 09:49:58 +03:00 |