yosys

Commit Graph

Author	SHA1	Message	Date
Icenowy Zheng	90d00182cf	anlogic: implement DRAM initialization As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>	2018-12-20 07:56:15 +08:00
Icenowy Zheng	d53a2bd1d3	anlogic: add support for Eagle Distributed RAM The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>	2018-12-17 23:20:40 +08:00

Author

SHA1

Message

Date

Icenowy Zheng

90d00182cf

anlogic: implement DRAM initialization

As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.

Now add the support by add a new pass to determine unknown values in the
initial value.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

2018-12-20 07:56:15 +08:00

Icenowy Zheng

d53a2bd1d3

anlogic: add support for Eagle Distributed RAM

The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

2018-12-17 23:20:40 +08:00

2 Commits