yosys

Commit Graph

Author	SHA1	Message	Date
whitequark	5157691f0e	write_cxxrtl: statically schedule comb logic and localize wires. This results in further massive gains in performance, modest decrease in compile time, and, for designs without feedback arcs, makes it possible to run eval() once per clock edge in certain conditions.	2020-04-09 04:08:36 +00:00
whitequark	d6d7273421	write_cxxrtl: elide wires for results of comb cells used once. This results in massive gains in performance, equally massive reduction in compile time, and improved readability.	2020-04-09 04:08:36 +00:00
whitequark	d20e971725	write_cxxrtl: new backend. This commit adds a basic implementation that isn't very performant but implements most of the planned features.	2020-04-09 04:08:36 +00:00

Author

SHA1

Message

Date

whitequark

5157691f0e

write_cxxrtl: statically schedule comb logic and localize wires.

This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.

2020-04-09 04:08:36 +00:00

whitequark

d6d7273421

write_cxxrtl: elide wires for results of comb cells used once.

This results in massive gains in performance, equally massive
reduction in compile time, and improved readability.

2020-04-09 04:08:36 +00:00

whitequark

d20e971725

write_cxxrtl: new backend.

This commit adds a basic implementation that isn't very performant
but implements most of the planned features.

2020-04-09 04:08:36 +00:00

3 Commits