Eddie Hung
509de98468
submod: revert accidental change
2020-05-14 10:33:56 -07:00
Eddie Hung
b66904e9cd
Revert "Merge branch 'eddie/kernel_makeblackbox' into eddie/abc9_auto_dff"
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This reverts commit e08497c7c9d8a6f7a3eccddf2149c45d9ecff207, reversing
changes made to e366fd55122236a21c6daee6765724add840a1f9.
2020-05-14 10:33:56 -07:00
Eddie Hung
f975cf39cb
xaiger: update help text
2020-05-14 10:33:56 -07:00
Eddie Hung
34c7732642
ecp5: add synth_ecp5 -dff to work with -abc9
2020-05-14 10:33:56 -07:00
Eddie Hung
e38b1280f9
abc9_ops: -prep_dff_map to warn if no specify cells
2020-05-14 10:33:56 -07:00
Eddie Hung
23c53a6bdd
ice40: synth_ice40 cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
5d5029fa75
ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init
2020-05-14 10:33:56 -07:00
Eddie Hung
039c3a5982
kernel: Module::makeblackbox() to clear connections + delete wires last
2020-05-14 10:33:56 -07:00
Eddie Hung
fe7965e0ee
ice40: add synth_ice40 -dff option, support with -abc9
2020-05-14 10:33:56 -07:00
Eddie Hung
4a10c87ae1
ice40: split out cells_map.v into ff_map.v
2020-05-14 10:33:56 -07:00
Eddie Hung
a1ae5845f8
abc9_ops: -prep_dff_map to cope with plain $_DFF_[NP]_ flops
2020-05-14 10:33:56 -07:00
Eddie Hung
c10757a8ea
synth_xilinx: rename dff_mode -> dff
2020-05-14 10:33:56 -07:00
Eddie Hung
90cd49995b
xaiger: do not treat (* init=1'bx *) as 1'b0
2020-05-14 10:33:56 -07:00
Eddie Hung
6b3aa91a2a
abc9: cleanup
2020-05-14 10:33:56 -07:00
Eddie Hung
edacb8f437
abc9_ops: do not use (* abc9_init *)
2020-05-14 10:33:56 -07:00
Eddie Hung
483a190c1b
aiger: -xaiger to parse initial state back into (* init *) on Q wire
2020-05-14 10:33:56 -07:00
Eddie Hung
77f3abcdc3
xaiger: when -dff use (* init *) for initial state
2020-05-14 10:33:56 -07:00
Eddie Hung
95763c8d18
abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes
2020-05-14 10:33:56 -07:00
Eddie Hung
accfc70fc2
abc9: fix behaviour and help for -box option
2020-05-14 10:33:56 -07:00
Eddie Hung
53fc3ed645
aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created
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according to mergeability class, and init state as cell attr
2020-05-14 10:33:56 -07:00
Eddie Hung
ffa52738fb
xaiger: output $_DFF_[NP]_ with mergeability if -dff option
2020-05-14 10:33:56 -07:00
Eddie Hung
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
Claire Wolf
f02e20907e
Merge pull request #2052 from YosysHQ/claire/verific_memfix
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Add support for non-power-of-two mem chunks in verific importer
2020-05-14 18:45:13 +02:00
Claire Wolf
140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes
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opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
2020-05-14 18:31:16 +02:00
Claire Wolf
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
Eddie Hung
56a5b1d2da
test: add another testcase as per @nakengelhardt
2020-05-14 08:36:36 -07:00
Claire Wolf
173aa27ca5
Add support for non-power-of-two mem chunks in verific importer
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-14 14:38:13 +02:00
Eddie Hung
5be4b00a0d
opt_clean: improve warning message
2020-05-14 00:59:38 -07:00
Eddie Hung
aa4a69f89b
opt_clean: add init test
2020-05-14 00:31:08 -07:00
Eddie Hung
fc9fb09a91
opt_clean: rminit without -purge; also remove if consistent with const..
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warn otherwise
2020-05-14 00:31:08 -07:00
Eddie Hung
68b31f5e99
opt_clean: really make 'clean' identical to 'opt_clean' by rminit too
2020-05-14 00:31:08 -07:00
Eddie Hung
237962debd
verilog: default to input in sv mode if task/func has no dir ...
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otherwise error
2020-05-13 13:33:37 -07:00
Eddie Hung
0d2c33f9f4
tests: update/extend task argument tests
2020-05-13 10:11:45 -07:00
Eddie Hung
27b7ffc754
ice40: fix ICESTORM_LC process sensitivity
2020-05-12 15:40:48 -07:00
Eddie Hung
4ecae8a673
ice40: fix whitespace
2020-05-12 15:40:13 -07:00
David Shah
95fb3cf487
ecp5: Add missing SERDES parameters
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Signed-off-by: David Shah <dave@ds0.me>
2020-05-12 21:12:26 +01:00
Eddie Hung
1f3003be7d
verilog: error out when non-ANSI task/func arguments
2020-05-11 13:00:36 -07:00
Eddie Hung
e5ce5a4fd5
tests: add #2042 testcase
2020-05-11 11:05:19 -07:00
Eddie Hung
b11cf67a81
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
Claire Wolf
aafaeb66df
Merge pull request #2038 from nakengelhardt/no-libdir-flag
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Remove yosys libdir from LDFLAGS (and fix a typo)
2020-05-08 10:40:25 +02:00
Claire Wolf
8ec3b6db1c
Fix clang compiler warning
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-08 10:13:39 +02:00
whitequark
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
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Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
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By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
N. Engelhardt
c9befa769f
Remove yosys libdir from LDFLAGS (and fix a typo)
2020-05-07 19:28:18 +02:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Eddie Hung
3a985d8285
Merge pull request #2034 from YosysHQ/eddie/abc_remote
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Makefile: git fetch $(ABCURL) explicitly for local ABC checkout
2020-05-07 08:07:42 -07:00
Xiretza
d86fc791f9
Reorder cases to avoid fall-through warning
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log_assert(false) never returns and thus can't fall through, but gcc
doesn't seem to think that far. Making it the last case avoids the
problem entirely.
2020-05-07 13:39:34 +02:00
Xiretza
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
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C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
Eddie Hung
8eb98b12c7
Makefile: git fetch all commits from $(ABCURL) repo
2020-05-06 16:23:46 -07:00
Eddie Hung
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00