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3,897 Commits 81 Branches 48 Tags 63 MiB
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22 Commits

Author SHA1 Message Date
Robert Ou 14e49fb057 coolrunner2: Add an ANDTERM/XOR between chained FFs 
In some cases (e.g. the low bits of counters) the design might end up
with a flip-flop whose input is directly driven by another flip-flop.
This isn't possible in the Coolrunner-II architecture, so add a single
AND term and XOR in this case.
 2018-03-31 03:54:48 -07:00
Robert Ou cfa3753b89 coolrunner2: Split multi-bit nets 
The PAR tool doesn't expect any "dangling" nets with no drivers nor
sinks. By splitting the nets, clean removes them.
 2018-03-31 02:56:11 -07:00
Robert Ou 8fe9cdf364 coolrunner2: Add extraction for TFFs 2018-03-31 02:54:26 -07:00
Robert Ou 2abcd98527 coolrunner2: Move LOC attributes onto the IO cells 2018-01-17 16:17:32 -08:00
Robert Ou 5f65e24ccb coolrunner2: Finish fixing special-use p-terms 2017-09-01 07:22:16 -07:00
Robert Ou fa04366f38 coolrunner2: Generate a feed-through AND term when necessary 2017-09-01 07:22:01 -07:00
Robert Ou 6775177171 coolrunner2: Initial fixes for special p-terms 
Certain signals can only be controlled by a product term and not a
sum-of-products. Do the initial work for fixing this.
 2017-09-01 07:21:51 -07:00
Robert Ou 7f08be4304 coolrunner2: Fix mapping of flip-flops 2017-09-01 07:21:39 -07:00
Robert Ou ac84f47829 coolrunner2: Combine some for loops together 2017-09-01 07:21:31 -07:00
Robert Ou 78fd24f40f coolrunner2: Add INVERT parameter to some BUFGs 2017-08-14 12:13:33 -07:00
Robert Ou 1e3ffd57cb coolrunner2: Add FFs with clock enable to cells_sim.v 2017-08-14 12:13:25 -07:00
Clifford Wolf 621787a9e0 Fix some c++ clang compiler errors 2017-07-03 19:38:30 +02:00
Clifford Wolf 5c1c126374 Apply minor coding style changes to coolrunner2 target 2017-07-03 19:35:40 +02:00
Robert Ou b102c0e254 coolrunner2: Add a few more primitives 
These cannot be inferred yet, but add them to cells_sim.v for now
 2017-06-25 23:58:28 -07:00
Robert Ou 36b75dfcb7 coolrunner2: Initial mapping of latches 2017-06-25 23:58:28 -07:00
Robert Ou 4af5baab21 coolrunner2: Initial mapping of DFFs 
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
 2017-06-25 23:58:28 -07:00
Robert Ou 1eb5dee799 coolrunner2: Remove redundant INVERT_PTC 2017-06-25 23:58:28 -07:00
Robert Ou ffff001008 coolrunner2: Remove debug prints 2017-06-25 23:58:28 -07:00
Robert Ou 5798105d47 coolrunner2: Correctly handle $_NOT_ after $sop 2017-06-25 23:58:28 -07:00
Robert Ou 908ce3fdce coolrunner2: Also construct the XOR cell in the macrocell 2017-06-25 23:58:28 -07:00
Robert Ou a64b56648d coolrunner2: Initial techmapping for $sop 2017-06-25 23:58:22 -07:00
Robert Ou 6e0fb889fa coolrunner2: Initial commit 2017-06-24 07:22:56 -07:00