Clifford Wolf
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468b8a5178
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Merge pull request #1419 from YosysHQ/eddie/lazy_derive
module->derive() to be lazy and not touch ast if already derived
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2019-10-03 12:06:12 +02:00 |
Clifford Wolf
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0e05424885
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Merge pull request #1422 from YosysHQ/eddie/aigmap_select
Add -select option to aigmap
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2019-10-03 11:54:04 +02:00 |
Clifford Wolf
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afdc990595
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Merge pull request #1429 from YosysHQ/clifford/checkmapped
Add "check -mapped"
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2019-10-03 11:50:53 +02:00 |
Clifford Wolf
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3e27b2846b
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Add "check -allow-tbuf"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-10-03 11:49:56 +02:00 |
David Shah
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e46e8753c8
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frontends/ast: code style
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:55:43 +01:00 |
David Shah
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9b9d24f15b
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sv: Improve tests
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:45 +01:00 |
David Shah
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5501d9090a
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sv: Fix typedefs in blocks
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:45 +01:00 |
David Shah
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8cc1bee33c
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sv: Disambiguate interface ports
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:45 +01:00 |
David Shah
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1746b6373b
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Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:45 +01:00 |
David Shah
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abc155715d
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sv: Add test scripts for typedefs
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:14 +01:00 |
David Shah
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c0bb47beca
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sv: Fix memories of typedefs
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:14 +01:00 |
David Shah
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497faf4ec0
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sv: Add %expect
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:14 +01:00 |
David Shah
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af25585170
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sv: Add support for memories of a typedef
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:14 +01:00 |
David Shah
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30d2326030
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sv: Add support for memory typedefs
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:14 +01:00 |
David Shah
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e70e4afb60
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sv: Fix typedefs in packages
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:14 +01:00 |
David Shah
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c962951612
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sv: Fix typedef parameters
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:14 +01:00 |
David Shah
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f6b5e47e40
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sv: Switch parser to glr, prep for typedef
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-03 09:54:14 +01:00 |
David Shah
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e0a6742935
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Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16
ecp5: Add support for mapping 36-bit wide PDP BRAMs
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2019-10-03 09:53:45 +01:00 |
Eddie Hung
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e9645c7fa7
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Fix broken CI, check reset even for constants, trim rstmux
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2019-10-02 21:26:26 -07:00 |
Eddie Hung
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278533fe59
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Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire
RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
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2019-10-02 19:40:39 -07:00 |
Eddie Hung
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e4bd5aaebf
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Fix test
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2019-10-02 18:12:25 -07:00 |
Eddie Hung
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c6a55d948a
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Merge branch 'eddie/fix_sat_init' into eddie/fix1427
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2019-10-02 18:07:38 -07:00 |
Eddie Hung
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f6fabc8fda
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Update test
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2019-10-02 18:03:45 -07:00 |
Eddie Hung
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d99810ad8a
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Refactor peepopt_dffmux and be sensitive to \init when trimming
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2019-10-02 18:01:45 -07:00 |
Eddie Hung
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e730a595ee
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Add test
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2019-10-02 18:01:41 -07:00 |
Eddie Hung
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62c66406ad
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log_dump() to support State enum
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2019-10-02 17:49:07 -07:00 |
Eddie Hung
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f46ac1df9f
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Be mindful that sigmap(wire) could have dupes when checking \init
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2019-10-02 16:08:46 -07:00 |
Eddie Hung
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c28d4b8047
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Add test that is expecting to fail
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2019-10-02 14:52:40 -07:00 |
Eddie Hung
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265a655ef9
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Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
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2019-10-02 12:43:35 -07:00 |
Eddie Hung
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a4f2f7d23c
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Extend test with renaming cells with prefix too
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2019-10-02 12:43:18 -07:00 |
Clifford Wolf
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6028f5df1a
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Merge pull request #1428 from YosysHQ/clifford/fixbtor
Fix btor back-end to use "state" instead of "input" for undef init bits
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2019-10-02 13:48:09 +02:00 |
Clifford Wolf
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45e4c040d7
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Add "check -mapped"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-10-02 13:35:03 +02:00 |
Clifford Wolf
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a84a2d74c7
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Fix btor back-end to use "state" instead of "input" for undef init bits
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-10-02 12:48:04 +02:00 |
Miodrag Milanović
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da347b9f7e
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Merge pull request #1426 from YosysHQ/mmicko/fix_environ
Define environ, fixes #1424
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2019-10-01 19:50:37 +02:00 |
Miodrag Milanovic
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c026579c20
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Define environ, fixes #1424
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2019-10-01 18:45:07 +02:00 |
David Shah
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b424d374db
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ecp5: Fix shuffle_enable port
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-01 14:14:46 +01:00 |
David Shah
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7a1538cd36
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ecp5: Add support for mapping 36-bit wide PDP BRAMs
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-01 13:46:36 +01:00 |
Sergey
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eb750670e3
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run-test.sh Move $x at end of line.
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2019-10-01 11:14:12 +03:00 |
Sergey
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e092c4ae6b
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Merge branch 'master' into SergeyDegtyar/efinix
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2019-10-01 11:04:32 +03:00 |
Sergey
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d99b1e3261
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Merge branch 'master' into SergeyDegtyar/anlogic
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2019-10-01 10:57:09 +03:00 |
Sergey
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fc56459746
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run-test.sh Move $x at end of line.
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2019-10-01 10:55:34 +03:00 |
Eddie Hung
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1caaf51492
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equiv_opt with -assert
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2019-09-30 19:54:59 -07:00 |
Eddie Hung
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f8d5e11aa7
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Update resource count for alu.ys
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2019-09-30 19:54:04 -07:00 |
Eddie Hung
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369652d4b9
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Add test
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2019-09-30 17:20:39 -07:00 |
Eddie Hung
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edc3780723
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techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
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2019-09-30 17:20:12 -07:00 |
Eddie Hung
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8b239ee707
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Add quick test
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2019-09-30 15:34:04 -07:00 |
Eddie Hung
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f2f19df2d4
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Add -select option to aigmap
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2019-09-30 15:26:29 -07:00 |
Eddie Hung
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d963e8c2c6
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Fix typo
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2019-09-30 15:18:40 -07:00 |
Eddie Hung
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d992858318
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Move $x to end as per 7f0eec8
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2019-09-30 15:15:14 -07:00 |
Eddie Hung
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eeb86247c5
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Update fsm.ys resource count
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2019-09-30 15:14:41 -07:00 |