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1349 Commits

Author SHA1 Message Date
Clifford Wolf 6514443a5c
Merge pull request #672 from daveshah1/fix_bram 
memory_bram: Reset make_outreg when growing read ports
 2018-10-19 16:09:11 +02:00
David Shah 3420ae5ca5 memory_bram: Reset make_outreg when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 14:46:31 +01:00
Clifford Wolf f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
tklam f4343b3dc7 stop check_signal_in_fanout from traversing FFs 2018-10-13 23:24:24 +08:00
tklam 302edf0429 stop check_signal_in_fanout from traversing FFs 2018-10-13 23:11:19 +08:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
tklam b86eb3deef fix bug: pass by reference 2018-09-26 17:57:39 +08:00
TK Lam 2b89074240 Fix issue #639 2018-09-26 16:11:45 +08:00
Clifford Wolf 592a82c0ad
Merge pull request #625 from aman-goel/master 
Minor revision to -expose in setundef pass
 2018-09-14 12:36:13 +02:00
acw1251 5fe16c25b8 Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
Aman Goel 75c1f8d241 Minor revision to -expose in setundef pass 
Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
 2018-09-10 21:44:36 -04:00
Clifford Wolf 05466790a6
Merge pull request #606 from cr1901/show-win 
`show` pass `-format` and `-viewer` improvements on Windows
 2018-08-19 15:25:46 +02:00
Aman Goel 83b41260f6 Revision to expose option in setundef pass 
Corrects indentation

Simplifications and corrections
 2018-08-18 09:08:07 +05:30
Aman Goel 61f002c908
Merge pull request #3 from YosysHQ/master 
Updates from official repo
 2018-08-18 08:18:40 +05:30
William D. Jones 7ce7ea2eb4 Update show pass documentation with Windows caveats. 2018-08-15 17:18:19 -04:00
William D. Jones 9f91c62348 Fix run_command() when using -format and -viewer in show pass. 2018-08-15 17:18:19 -04:00
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf 0eaab6cd1d Add missing <deque> include (MSVC build fix) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 15:21:59 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf 87aef8f0cc Add async2sync pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-19 15:31:12 +02:00
Aman Goel 5dcb899e76
Merge pull request #2 from YosysHQ/master 
Merging with official repo
 2018-07-18 11:34:18 -04:00
David Shah 459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
Aman Goel 4d343fc1cd Merging with official repo 2018-07-04 15:14:28 -04:00
Clifford Wolf 5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf 675a44b41a Be slightly less aggressive in "deminout" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-19 14:29:38 +02:00
Edmond Cote d89560a0ba
Include module name for area summary stats 
The PR prints the name of the module when displaying the final area count.

Pros:
- Easier for the user to `grep` for area information about a specific module

Cons:
- Arguably more verbose, less "pretty" than author desires

Verification:
~~~~
30c30
<    Chip area for this module: 20616.349000
---
>    Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
<    Chip area for this module: 88.697700
---
>    Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
<    Chip area for this module: 20705.046700
---
>    Chip area for top module '\picorv32_axi': 20705.046700
~~~~
 2018-06-18 17:29:01 -07:00
Clifford Wolf f273291dfe Add setundef -anyseq / -anyconst support to -undriven mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 11:57:28 +02:00
Clifford Wolf 4cd6d5556a Add "setundef -anyconst" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 11:49:58 +02:00
Clifford Wolf 3ab79a231b Bugfix in handling of array instances with empty ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-31 18:09:31 +02:00
Clifford Wolf cee4b1e6bc Disable memory_dff for initialized FFs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 17:16:15 +02:00
Clifford Wolf 74efafc1cf Add some cleanup code to memory_nordff 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 16:42:06 +02:00
Robert Ou 9763e4d830 Fix infinite loop in abc command under emscripten 2018-05-18 22:42:39 -07:00
Robert Ou bfce3a7479 Add an option to statically link abc into yosys 
This is currently incomplete because the output filter no longer works.
 2018-05-18 22:35:28 -07:00
Aman Goel 6e63df6dd0 Correction to -expose with setundef 2018-05-15 13:06:23 -04:00
Clifford Wolf fe80b39f56 Fix iopadmap for loops between tristate IO buffers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 14:02:27 +02:00
Clifford Wolf edd297fb1c Fix iopadmap for cases where IO pins already have buffers on them 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 13:13:43 +02:00
Aman Goel 8b9a8c7f91 Minor correction 
Minor typo error correction in -expose with setundef
 2018-05-14 18:58:49 -04:00
Aman Goel b4a303a1b7 Corrections to option -expose in setundef pass 2018-05-13 20:13:54 -04:00
Aman Goel 9286acb687 Add option -expose to setundef pass 
Option -expose converts undriven wires to inputs.

Example usage: setundef -undriven -expose [selection]
 2018-05-13 16:53:35 -04:00
Clifford Wolf 0fad1570b5 Some cleanups in setundef.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-13 16:36:12 +02:00
Christian Krämer c1ecb1b2f1 Add "#ifdef __FreeBSD__" 
(Re-commit e3575a8 with corrected author field)
 2018-05-13 13:08:26 +02:00
Clifford Wolf 1167538d26 Revert "Add "#ifdef __FreeBSD__"" 
This reverts commit e3575a86c5.
 2018-05-13 13:06:36 +02:00
Clifford Wolf 587056447e Add optimization of tristate buffer with constant control input 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 15:18:27 +02:00
Clifford Wolf 11406a8082 Add "hierarchy -simcheck" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 13:59:13 +02:00
Johnny Sorocil e3575a86c5 Add "#ifdef __FreeBSD__" 2018-05-05 13:02:44 +02:00
Clifford Wolf 145c685de0 Add ABC FAQ to "help abc" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-04 21:59:31 +02:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Clifford Wolf 705c366a91 Added missing dont_use handling for SR FFs to dfflibmap 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-05 11:01:45 +02:00
Clifford Wolf 665eec3d53 Removed $timescale from "sat" command VCD writer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-29 12:38:41 +02:00
Clifford Wolf ee3c12d6d9 Chenged "extensions_map" to "extensions_list" in hierarchy.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 14:12:57 +02:00
Sergi Granell f93f8aaa11 passes/hierarchy: Reduce code duplication in expand_module 
This also makes it easier to add new file extensions support.

Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com>
 2018-03-27 09:35:20 +02:00
Clifford Wolf 491c352da7 Add .sv support to "hierarchy -libdir" 2018-03-26 21:19:00 +02:00
Clifford Wolf 08225f49a4 Add "expose -input" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-12 13:52:52 +01:00
Clifford Wolf 83ffb23739 Add "setundef -undef" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-12 13:52:35 +01:00
Clifford Wolf a74f805ba0 Fix handling of src attributes in flatten 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 13:55:30 +01:00
Clifford Wolf 73c01dca65 Add "memory_nordff" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 23:31:51 +01:00
Clifford Wolf 61a9e2eeb3 Fix connwrappers help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 22:54:34 +01:00
Clifford Wolf d31584c649 Add $dlatchsr support to clk2fflogic 2018-02-26 12:20:28 +01:00
Clifford Wolf fba499b866 Fix opt_rmdff handling of $dlatchsr 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 11:46:05 +01:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf 717abc93a8 Recognize stand-alone obj pattern even when it contains a slash 2018-02-13 14:55:24 +01:00
Clifford Wolf 9337e4999d Improve log messages in equiv_make 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-19 16:20:40 +01:00
Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-09 18:42:19 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf 446ccf1f05 Bugfix in hierarchy blackbox module port width handling 2018-01-07 16:35:22 +01:00
Clifford Wolf c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf fefb652d56
Merge pull request #480 from Fatsie/liberty_value_expression 
Value of properties can be expression.
 2018-01-04 13:30:00 +01:00
Clifford Wolf 2d140a44eb Temporarily derive blackbox modules in hierarchy to evaluate port widths 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-04 13:23:29 +01:00
Staf Verhaegen 92eb841f0a Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:37:17 +00:00
Clifford Wolf 6132e6e72a Fix a bug in clk2fflogic memory handling 2017-12-14 03:05:55 +01:00
Clifford Wolf 590e6961cb Add clk2fflogic memory support 2017-12-14 02:07:31 +01:00
Clifford Wolf 88182e46d7 Check for memories in clk2fflogic 2017-12-13 19:14:34 +01:00
Clifford Wolf ca2adc30c9 Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
Clifford Wolf 9ae25039fb Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
Clifford Wolf 4f31cb6dad Add "ltp" command 2017-10-31 12:40:25 +01:00
Clifford Wolf c238f45ecf Fix memory corruption bug in opt_rmdff 2017-10-26 18:02:15 +02:00
Clifford Wolf 1e502ef5a0 Fix typo in opt_clean log message 2017-10-26 18:01:48 +02:00
Clifford Wolf 716dbc9274 Revert 90be0d8 as it causes endless loops for some designs 2017-10-14 11:57:25 +02:00
Kaj Tuomi 90be0d800b Fix input vector for reduce cells. 2017-10-12 13:05:10 +03:00
Clifford Wolf 7c57d8fbb4 Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
Clifford Wolf 3f22f48eeb Add blackbox command 2017-10-04 18:30:42 +02:00
Andrew Zonenberg 2b65b65d70 Added missing "break" 2017-09-15 17:54:52 -07:00
Andrew Zonenberg 7b3966714c Implemented off-chain support for extract_reduce 2017-09-15 13:59:18 -07:00
Andrew Zonenberg 3404934c9c extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored. 2017-09-15 13:59:05 -07:00
Clifford Wolf ce78717e36 Merge pull request #412 from azonenberg/reduce-fixes 
extract_reduce: Fix segfault on "undriven" inputs
 2017-09-14 22:36:25 +02:00
Robert Ou ab1bf8d661 extract_reduce: Fix segfault on "undriven" inputs 
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
 2017-09-14 12:54:44 -07:00
Clifford Wolf 498526cc0b Merge pull request #411 from azonenberg/counter-extraction-fixes 
Various improvements and bug fixes to extract_counter
 2017-09-14 21:44:26 +02:00
Andrew Zonenberg 66e8986ae7 Minor changes to opt_demorgan requested during code review 2017-09-14 10:35:25 -07:00
Andrew Zonenberg 367d6b2194 Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output 2017-09-14 10:27:10 -07:00
Andrew Zonenberg c8f2f082c6 Added support for inferring counters with reset to full scale instead of zero 2017-09-14 10:26:43 -07:00
Andrew Zonenberg 122532b7e1 Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
Andrew Zonenberg 0484ad666d Added support for inferring counters with active-low reset 2017-09-14 10:26:21 -07:00
Andrew Zonenberg a84172b23b Initial support for extraction of counters with clock enable 2017-09-14 10:26:10 -07:00
Andrew Zonenberg c4a70a8cc3 Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters. 2017-09-14 10:25:51 -07:00
Andrew Zonenberg 6da5d36968 Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved 2017-09-12 18:47:46 -07:00
Clifford Wolf f9d023c53f Add src attribute to extra cells generated by proc_dlatch 2017-09-09 10:18:08 +02:00
Clifford Wolf 7d41c5e177 Further improve extract_fa (but still buggy) 2017-09-02 16:39:17 +02:00
Clifford Wolf 18609f3df8 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-09-01 12:35:09 +02:00