Clifford Wolf
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1282a113da
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Fixed supply0/supply1 with many wires
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2014-12-11 13:56:20 +01:00 |
Clifford Wolf
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87333f3ae2
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Added warning for use of 'z' constants in HDL
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2014-11-14 19:59:50 +01:00 |
Clifford Wolf
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4e5350b409
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Fixed parsing of nested verilog concatenation and replicate
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2014-11-12 19:10:35 +01:00 |
Clifford Wolf
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a21481b338
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Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
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2014-10-30 14:01:02 +01:00 |
Clifford Wolf
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f9c096eeda
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Added support for task and function args in parentheses
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2014-10-27 13:21:57 +01:00 |
William Speirs
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fad0b0c506
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Updated lexers & parsers to include prefixes
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2014-10-15 00:48:19 +02:00 |