riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2,343 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

197 Commits

Author SHA1 Message Date
Clifford Wolf 546e8b5fe7 Improved TopoSort determinism 2014-11-07 15:21:03 +01:00
Clifford Wolf 84ffe04075 Fixed various VS warnings 2014-10-18 15:20:38 +02:00
Clifford Wolf 973d376733 Added genfiles.zip to MXE "make dist" 2014-10-17 12:11:15 +02:00
Clifford Wolf c21c9dab1e Removed CHECK() macro from libparse.cc (was using non-std c features) 2014-10-13 17:22:06 +02:00
Clifford Wolf 54bf3a95dd More Win32 build fixes 2014-10-10 18:34:19 +02:00
Clifford Wolf bbd808072b Added format __attribute__ to stringf() 2014-10-10 17:22:08 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf ccf7b2e342 Added mxe-based cross build for win32 2014-10-09 10:50:44 +02:00
Clifford Wolf 696d7ed40e Fixes in "hilomap" help message 2014-10-08 21:38:37 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf b86410b2ab More aggressive $macc merging in alumacc 2014-09-15 12:42:11 +02:00
Clifford Wolf b470c480e9 Added the obvious optimizations to alumacc $macc generator 2014-09-15 12:22:03 +02:00
Clifford Wolf fcbda07411 Improved maccmap tree bit packing 2014-09-15 12:00:19 +02:00
Clifford Wolf 7e156a5419 Fixed techmap_wrap for techmap_celltype 2014-09-14 15:34:36 +02:00
Clifford Wolf 014bb34e0e Various fixes/cleanups in alumacc and maccmap 2014-09-14 14:49:53 +02:00
Clifford Wolf 124e759280 Added techmap_wrap attribute 2014-09-14 14:49:26 +02:00
Clifford Wolf b34ca15185 alumacc fix for $pos cells 2014-09-14 14:00:14 +02:00
Clifford Wolf 0df1d9ad72 Extract $alu cells in alumacc 2014-09-14 13:23:44 +02:00
Clifford Wolf 7b16c63101 Merge $macc cells in alumacc pass 2014-09-14 11:21:37 +02:00
Clifford Wolf 0b72f0acb1 Basic $macc extract in alumacc 2014-09-14 10:45:28 +02:00
Clifford Wolf ff157fb74f alumacc skeleton 2014-09-14 10:02:00 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf 1a88e47396 Trim msb/lsb zero bits from full adder in maccmap 2014-09-08 11:21:58 +02:00
Clifford Wolf c50b841b29 Added 'techmap_maccmap' techmap attribute 2014-09-07 18:23:37 +02:00
Clifford Wolf 015dcdc84c Added "maccmap" command 2014-09-07 18:23:04 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf 826fdb34d8 Added "techmap -autoproc" 2014-09-01 15:36:29 +02:00
Clifford Wolf d148b0af0d Fixed inserting of Q-inverters in dfflibmap 2014-08-27 19:44:12 +02:00
Clifford Wolf c642dd0b3e Only call proc_share_dirname() in techmap when necessary 2014-08-23 15:32:00 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf 410d043dd8 Renamed toposort.h to utils.h 2014-08-17 00:55:35 +02:00
Clifford Wolf 674f421b47 Bugfix in iopadmap 2014-08-15 14:29:42 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00
Clifford Wolf d320e75087 document "techmap -map %<design-name>" 2014-08-15 02:01:30 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 014a41fcf3 Implemented recursive techmap 2014-08-03 12:40:43 +02:00
Clifford Wolf 08ec33a5e5 Implemented simplemap support for "techmap -extern" 2014-08-02 21:55:13 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 6ca0c569d9 Added "techmap -assert" 2014-07-31 02:21:41 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 8b0f50792c Added techmap -extern 2014-07-27 21:31:18 +02:00
Clifford Wolf 5da343b7de Added topological sorting to techmap 2014-07-27 16:43:39 +02:00
Clifford Wolf 49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf 45b4154b37 Added "make SMALL=1" 2014-07-24 19:03:57 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 361e0d62ff Replaced depricated NEW_WIRE macro with module->addWire() calls 2014-07-21 12:42:02 +02:00
Clifford Wolf 1d88f1cf9f Removed deprecated module->new_wire() 2014-07-21 12:35:06 +02:00
Clifford Wolf 8d04ca7d22 Added call_on_selection() and call_on_module() API 2014-07-20 15:33:06 +02:00
Clifford Wolf b76bf05cda Added support for "blackbox" attribute to iopadmap 2014-07-17 08:59:07 +02:00
Clifford Wolf 64a6906cc4 Added support for "blackbox" attribute to flatten/techmap 2014-07-17 08:58:51 +02:00
Johann Glaser 684c85902d be more verbose when techmap yielded processes 2014-05-26 17:13:41 +02:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Siesh1oo 8127d5e8c3 - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). 
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
 - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
 2014-03-12 23:17:14 +01:00
Clifford Wolf 9087ece97c OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:52:37 +01:00
Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf fcae92868d Fixed dumping of timing() { .. } block in libparse 2014-03-09 15:16:07 +01:00
Clifford Wolf 1ecaf1bb76 Added techmap -max_iter option 2014-03-06 12:15:17 +01:00
Clifford Wolf 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap 2014-02-20 23:42:07 +01:00
Clifford Wolf 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." 2014-02-20 23:31:13 +01:00
Clifford Wolf 236fc4209c Added "extract -map %<design_name>" 2014-02-20 23:30:15 +01:00
Clifford Wolf a71d09421d Added techmap support for _TECHMAP_CONNMAP_*_ 2014-02-18 19:51:00 +01:00
Clifford Wolf ca53ef5098 Better preserve wires when flattening (in comparison to techmap) 2014-02-17 09:44:39 +01:00
Clifford Wolf 6d63f39eb6 Added some additional checks to techmap 2014-02-16 22:18:06 +01:00
Clifford Wolf a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap 2014-02-16 21:58:59 +01:00
Clifford Wolf d3dc22a90f Added recursion support to techmap 2014-02-16 17:16:44 +01:00
Clifford Wolf 623a68f528 Added iopadmap -bits 2014-02-15 21:59:26 +01:00
Clifford Wolf cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff 2014-02-15 16:34:12 +01:00
Clifford Wolf 6644f80d97 Moved some passes to other source directories 2014-02-08 14:39:15 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf c13c5b9b7b Changed techmap description from "simple" to "generic" 2014-02-06 13:10:06 +01:00
Clifford Wolf c1ed2607fb Added support for // comments in liberty parser 2014-01-25 06:32:16 +01:00