yosys

Commit Graph

Author	SHA1	Message	Date
Clifford Wolf	53655d173b	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
Clifford Wolf	bd10927f45	Progress in cell library documentation	2016-02-01 13:58:10 +01:00
Clifford Wolf	bbcbf739e6	Progress on cell help messages	2015-10-20 16:49:11 +02:00
Clifford Wolf	5d1c0ce7c0	Progress on cell help messages	2015-10-17 02:35:19 +02:00
Clifford Wolf	87adb523aa	Added more cell descriptions	2015-10-14 20:30:59 +02:00
Clifford Wolf	7d3a3a3173	Added first help messages for cell types	2015-10-14 16:27:42 +02:00
Clifford Wolf	d5b1a90b33	Added $tribuf and $_TBUF_ sim models	2015-08-16 13:05:32 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes Smaller this time	2015-08-14 23:27:05 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	706631225e	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	2015-04-05 09:45:14 +02:00
Clifford Wolf	fad9cec47b	Added $_DFFE_??_ cell types	2014-12-08 10:43:38 +01:00
Clifford Wolf	c3e779a65f	Added $_BUF_ cell type	2014-10-03 10:12:28 +02:00
Clifford Wolf	47c2637a96	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_	2014-08-16 18:29:39 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	1202f7aa4b	Renamed "stdcells.v" to "techmap.v"	2014-07-31 02:32:00 +02:00
Clifford Wolf	d4a1b0af5b	Added support for dlatchsr cells	2014-03-31 14:14:40 +02:00
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00

17 Commits