riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
6,319 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

196 Commits

Author SHA1 Message Date
Eddie Hung 42e40dbd0a Merge remote-tracking branch 'origin/master' into ice40dsp 2019-07-18 15:45:25 -07:00
Eddie Hung 2339b7fc37 mul2dsp to create cells that can be interchanged with $mul 2019-07-18 15:37:35 -07:00
Eddie Hung e22a752242 Make consistent 2019-07-18 15:21:23 -07:00
Eddie Hung 8326af5418 Fix signed multiplier decomposition 2019-07-18 13:11:26 -07:00
Eddie Hung 2024357f32 Working for unsigned 2019-07-18 10:53:18 -07:00
Eddie Hung d5cd2c80be Cleanup 2019-07-18 09:20:48 -07:00
David Shah 16b0ccf04c mul2dsp: Lower partial products always have unsigned inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-18 11:33:37 +01:00
Eddie Hung 8dca8d486e Fix mul2dsp signedness 2019-07-17 12:44:52 -07:00
Eddie Hung 1b62b82e05 A_SIGNED == B_SIGNED so flip both 2019-07-17 11:34:18 -07:00
Eddie Hung 0b6d47f8bf Add DSP_{A,B}_SIGNEDONLY macro 2019-07-16 15:55:13 -07:00
Eddie Hung 569cd66764 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-16 14:18:36 -07:00
Eddie Hung 7a58ee78dc gen_lut to return correctly sized LUT mask 2019-07-16 12:45:29 -07:00
David Shah 8da4c1ad82 mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:44:40 +01:00
David Shah 7a75f5f3ac mul2dsp: Fix indentation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:19:32 +01:00
Eddie Hung fd5b3593d8 Do not swap if equals 2019-07-15 16:52:37 -07:00
Eddie Hung 42f8e68e76 OUT port to Y in generic DSP 2019-07-15 14:45:47 -07:00
Eddie Hung 91fcf034bc Only swap if B_WIDTH > A_WIDTH 2019-07-15 11:24:11 -07:00
Eddie Hung 1793e6018a Tidy up 2019-07-15 11:19:54 -07:00
Eddie Hung 713337255e
Revert "Add "synth -keepdc" option" 2019-07-09 10:14:23 -07:00
Eddie Hung dd9771cbcd Add synth -keepdc option 2019-07-08 19:14:54 -07:00
David Shah e78864993a mul2dsp: Fix typo 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 18:42:41 +01:00
David Shah 269ff450f5 Add mul2dsp multiplier splitting rule and ECP5 mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 18:42:09 +01:00
Eddie Hung 627a62a797 Make doc consistent 2019-06-14 10:32:46 -07:00
Eddie Hung f7a9769c14 Merge remote-tracking branch 'origin/master' into xaig 2019-06-12 08:50:39 -07:00
Clifford Wolf c4b8575f43 Add "wreduce -keepdc", fixes #1016 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-20 15:36:13 +02:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Clifford Wolf d2d402e625 Run "peepopt" in generic "synth" pass and "synth_ice40" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 08:10:37 +02:00
Clifford Wolf 64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00
Clifford Wolf 4575e4ad86 Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:18:04 +02:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf a7e11261bd Add $specify2 and $specify3 cells to simlib 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Eddie Hung 45ddd9066e synth to take -abc9 argument 2019-02-20 11:08:49 -08:00
Clifford Wolf da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut 
synth: add k-LUT mode
 2019-01-02 15:44:57 +01:00
Clifford Wolf 00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut 
cmp2lut: new techmap pass
 2019-01-02 15:43:10 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
whitequark 18174202a9 synth: add k-LUT mode. 2019-01-02 08:25:03 +00:00
whitequark fdff32dd73 synth: improve script documentation. NFC. 2019-01-02 08:05:44 +00:00
whitequark a91892bba4 cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
whitequark 12596b5003 Fix typo. 2018-12-05 17:13:27 +00:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf 7fecc3c199 Make -nordff the default in "prep" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 13:17:09 +02:00
Clifford Wolf 27dd500d31 Add "synth -noshare" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 17:13:45 +01:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf b66d50e62d Fix minor typo in "prep" help message 2017-12-19 21:44:05 +01:00
Clifford Wolf e7a984a4df Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00