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628 Commits

Author SHA1 Message Date
N. Engelhardt 8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail 2024-09-23 15:19:48 +02:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Martin Povišer 34572708d5
Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode 
internal_stats: astnode (sizeof)
 2024-09-11 12:21:29 +02:00
Emil J. Tywoniak 1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Hoa Nguyen c1205ebc42 Initialize area stats in stat pass 
Currently, the area variables in the stat struct are not initialized.
This caused the area stats occasionally being an erroneous value.

Signed-off-by: Hoa Nguyen <hnpl@google.com>
 2024-09-07 21:30:58 -07:00
Miodrag Milanović b20df72e1e
Merge pull request #4536 from YosysHQ/functional 
Functional Backend
 2024-09-06 10:05:04 +02:00
Emil J. Tywoniak 14b9155492 internal_stats: fix doc build by adding a help string 2024-09-05 11:22:21 +02:00
Emil J. Tywoniak 0ce7631956 internal_stats: init, report current memory consumption on linux and mac 2024-09-03 19:28:24 +02:00
Emily Schmidt 850b3a6c29 convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h 2024-08-21 11:04:08 +01:00
Emily Schmidt 8c0f625c3a functional backend: topological sort starts with the output and next states nodes, other nodes get deleted 2024-08-21 11:03:29 +01:00
Emily Schmidt dd5ec84a26 fix bugs in drivertools 2024-08-21 11:01:09 +01:00
Jannis Harder d4e3daa9d0 ComputeGraph datatype for the upcoming functional backend 2024-08-21 11:01:09 +01:00
Jannis Harder 68c3a47945 WIP temporary drivertools example 2024-08-21 11:01:08 +01:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Martin Povišer 4c3203866f exec: Add missing newline 2024-08-07 13:02:00 +02:00
Emil J. Tywoniak 4b29f64142 cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter 2024-07-29 10:26:02 +02:00
Martin Povišer 0cefe8a1e8 check: Skip detailed edge modeling if costly 2024-07-18 13:08:19 +02:00
Martin Povišer e70b1251ad check: Adjust prints 2024-07-18 13:08:19 +02:00
Martin Povišer 3f71bc469d check: Rephrase comment 2024-07-18 13:08:19 +02:00
Miodrag Milanovic 9b82a44d25 Fix help message typo 2024-06-07 08:26:59 +02:00
Martin Povišer 4b67f3757f
Merge pull request #4404 from YosysHQ/povik/bbox_derive 
box_derive: New command to derive modules for boxes
 2024-05-31 19:09:18 +02:00
Martin Povišer b230c95cc4 select: Adjust help 2024-05-29 20:41:56 +02:00
Martin Povišer 49906be776 select: Introduce `-assert-mod-count` 2024-05-21 16:34:38 +02:00
Martin Povišer adc1a01490 select: Refactor some flag validation 2024-05-21 16:29:20 +02:00
Martin Povišer c0a196173a Rename `bbox_derive` to `box_derive` 2024-05-21 16:18:03 +02:00
Martin Povišer 5c929a91c2 bbox_derive: Write help 2024-05-21 14:57:37 +02:00
Martin Povišer 88af059fad bbox_derive: Fix `done` base type confusion 2024-05-21 14:57:26 +02:00
Emil J. Tywoniak 44b0fdc2bf bbox_derive: add assert and debug print 2024-05-03 20:43:01 +02:00
Emil J. Tywoniak e8c58a5528 bbox_derive: fix unininitialized memory UB when run with no named args 2024-05-03 20:41:42 +02:00
Martin Povišer 4c000d3aba Add new `bbox_derive` command for blackbox derivation 2024-05-03 20:39:11 +02:00
Martin Povišer b00abe4a26 Extend `log` command with `-push`, `-pop`, `-header` options 2024-04-10 11:49:20 +02:00
Martin Povišer 47931f9050
Merge pull request #4295 from gadfort/add-ports-stat 
add port statistics to stat command
 2024-04-08 11:12:02 +02:00
Peter Gadfort 160e3e089a add port statistics to stat command 2024-03-22 09:20:20 -04:00
Martin Povišer 206d894c56 check: Omit private wires in loop report 2024-03-11 10:45:36 +01:00
Martin Povišer d01728aaa5 celledges: Register async FF paths 2024-03-11 10:45:36 +01:00
Martin Povišer 4fdcf388d3 check: Assert edges data is not out-of-bounds 2024-03-11 10:45:17 +01:00
Martin Povišer b6112b3551 check: Consider read ports in loop detection 2024-03-11 10:45:17 +01:00
Martin Povišer fa74d0bd1a check: Use cell edges data in detecting combinational loops 2024-03-11 10:43:49 +01:00
Martin Povišer c5ae74af34 check: Improve found loop logging 
Print the detected loop in-order, and include source location for each
node, if available.
 2024-03-11 10:43:49 +01:00
Jannis Harder d8cdc213a6 rename -witness: Bug fix and rename formal cells 
Rename formal cells in addition to witness signals. This is required to
reliably track individual property states for the non-smtbmc flows.

Also removes a misplced `break` which resulted in only partial witness
renaming.
 2024-03-04 16:53:03 +01:00
Miodrag Milanović a3c81f4d62
Merge pull request #4216 from YosysHQ/show_href 
show: Add option to add cell/wire "src" attribute into graphviz attribute href
 2024-02-19 20:50:53 +01:00
N. Engelhardt 4b99db0b73
Merge pull request #4177 from povik/connect-extra_args 
connect: Do interpret selection arguments
 2024-02-19 15:18:37 +01:00
Ethan Mahintorabi b8a1009de9
Update passes/cmds/stat.cc 
Make reporting line more clear about the non cumulative area of sequential cells

Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
 2024-02-16 07:44:09 -08:00
Ethan Mahintorabi f0df0e3912
update type and variable names 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-16 00:01:44 +00:00
Ethan Mahintorabi 2d8343d423
update type and variable names 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-15 23:59:19 +00:00
Miodrag Milanovic 834276a2f7 show: Add option to add cell/wire "src" attribute into graphviz attribute href 2024-02-14 09:50:53 +01:00
Ethan Mahintorabi 8566489d85
stat: Add sequential area output to stat -liberty 
Checks to see if a cell is of type ff in the liberty,
and keeps track of an additional area value.

```
   Chip area for module '\addr': 92.280720
   Sequential area for module '\addr': 38.814720
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-09 23:51:00 +00:00
Claire Xen 1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite 
Add API to overwrite existing pass from plugin
 2024-02-05 23:49:24 +01:00
Jannis Harder 6c4902313b chformal: Support $check cells and add chformal -lower 
This adds support for `$check` cells in chformal and adds a `-lower`
mode which converts `$check` cells into `$assert` etc. cells with a
`$print` cell to output the `$check` message.
 2024-02-01 20:10:39 +01:00