Clifford Wolf
ce6695e22c
Fix $global_clock handling vs autowire
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 10:38:13 -08:00
Clifford Wolf
65412466c5
Merge pull request #847 from YosysHQ/clifford/fix785
...
Fix $readmem[hb] for mem2reg memories, fixes #785
2019-03-02 10:27:58 -08:00
Clifford Wolf
5d93dcce86
Fix $readmem[hb] for mem2reg memories, fixes #785
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 09:58:20 -08:00
Clifford Wolf
f2f5ecd834
Merge pull request #843 from YosysHQ/clifford/mem2regconstidx
...
Use mem2reg on memories that only have constant-index write ports
2019-03-02 08:40:54 -08:00
Clifford Wolf
67b78ea4fb
Merge pull request #845 from YosysHQ/clifford/travisnomacos
...
Disable macOS builds in Travis
2019-03-02 08:40:17 -08:00
Clifford Wolf
f75aee87e3
Disable macOS builds in Travis
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 08:29:28 -08:00
Larry Doolittle
57f8bb471f
Try again for passes/pmgen/ice40_dsp_pm.h rule
...
Tested on both in-tree and out-of-tree builds
2019-03-01 20:20:53 -08:00
Keith Rothman
3e16f75bc6
Revert FF models to include IS_x_INVERTED parameters.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb
Use singular for disabling of DRAM or BRAM inference.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:35:14 -08:00
Clifford Wolf
a02d61576e
Minor improvements in README
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 14:29:17 -08:00
Clifford Wolf
7cfae2c52f
Use mem2reg on memories that only have constant-index write ports
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 13:35:09 -08:00
Clifford Wolf
03237de686
Fix "write_edif -gndvccy"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 12:59:07 -08:00
Keith Rothman
eccaf101d8
Modify arguments to match existing style.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54
Changes required for VPR place and route synth_xilinx.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:02:27 -08:00
Clifford Wolf
66fd6396d4
Merge pull request #841 from mmicko/master
...
Fix ECP5 cells_sim for iverilog
2019-03-01 10:53:23 -08:00
Miodrag Milanovic
ca2b3feed8
Fix ECP5 cells_sim for iverilog
2019-03-01 19:25:23 +01:00
Clifford Wolf
60e3c38054
Improve "read" error msg
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:34:42 -08:00
Clifford Wolf
a82a7eb42e
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
...
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 20:27:27 -08:00
Clifford Wolf
b84febafd7
Hotfix for "make test"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:26:54 -08:00
Clifford Wolf
35e7f9979e
Merge pull request #837 from YosysHQ/clifford/fix835
...
Fix multiple issues in wreduce FF handling, fixes #835
2019-02-28 17:40:38 -08:00
Clifford Wolf
e847690bda
Fix multiple issues in wreduce FF handling, fixes #835
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 17:24:46 -08:00
Elms
cd2902ab1f
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
...
EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
2019-02-28 16:23:40 -08:00
Clifford Wolf
f505a41b76
Merge pull request #834 from YosysHQ/clifford/siminit
...
Add "write_verilog -siminit"
2019-02-28 15:03:55 -08:00
Clifford Wolf
241901461a
Add "write_verilog -siminit"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 15:03:03 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
68a6937173
Fix pmgen for in-tree builds
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 14:56:05 -08:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve
...
ECP5 Improvements
2019-02-28 14:46:56 -08:00
Clifford Wolf
6d143c9a01
Merge pull request #827 from ucb-bar/firrtlfixes
...
Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-28 14:45:04 -08:00
Clifford Wolf
64d91219b4
Fix pmgen for out-of-tree build
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 14:00:58 -08:00
Clifford Wolf
069801e441
Merge pull request #833 from YosysHQ/clifford/fix831
...
Fix smt2 code generation for partially initialized memory words, fixe…
2019-02-28 13:40:27 -08:00
Clifford Wolf
f570aa5e1d
Fix smt2 code generation for partially initialized memowy words, fixes #831
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 12:15:58 -08:00
Clifford Wolf
5e94a8a127
Merge pull request #832 from YosysHQ/supercover
...
Add "supercover" pass
2019-02-28 12:08:01 -08:00
Clifford Wolf
63be3f3bab
Improvements in "supercover" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:45:13 -08:00
Clifford Wolf
a58dbcf2ba
Add "supercover" skeleton
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:37:08 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
dfb23a79dd
Uncomment out more tests
2019-02-26 12:18:48 -08:00
Eddie Hung
7cac3b1c8b
abc9 -- multiple connections for inouts
2019-02-26 12:18:28 -08:00
Eddie Hung
8e883d92ed
write_xaiger to behave for undriven/unused inouts
2019-02-26 12:17:51 -08:00
Eddie Hung
da076344cc
parse_xaiger() to really pass single and multi-bit inout tests
2019-02-26 12:04:45 -08:00
Eddie Hung
3ea0161ae7
Add IdString::ends_with()
2019-02-26 12:04:16 -08:00
Eddie Hung
66b5f5166b
Enable two inout tests
2019-02-26 11:39:17 -08:00
Eddie Hung
8f02c846f6
parse_xaiger() to cope with multi bit inouts
2019-02-26 11:37:34 -08:00
Larry Doolittle
7a40294e93
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
Eddie Hung
967297cd57
abc9 cleanup
2019-02-25 18:40:53 -08:00
Eddie Hung
316232a7dd
parse_xaiger() to untransform $inout.out output ports
2019-02-25 18:40:23 -08:00
Eddie Hung
c492a3a1c4
write_xaiger duplicate inout port into out port with $inout.out suffix
2019-02-25 18:39:36 -08:00
Jim Lawson
171c425cf9
Fix FIRRTL to Verilog process instance subfield assignment.
...
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
2019-02-25 16:18:13 -08:00
Eddie Hung
721f6a14fb
read_aiger to accept empty string for clk_name, passable only if no latches
2019-02-25 15:34:02 -08:00
Eddie Hung
0ca3fd6a1c
abc9 not to clean after aigmap
2019-02-25 15:31:52 -08:00