Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
Clifford Wolf
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946ddff9ce
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Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26 20:12:50 +02:00 |
Clifford Wolf
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97a59851a6
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Added RTLIL::Cell::has(portname)
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2014-07-26 16:11:28 +02:00 |
Clifford Wolf
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f8fdc47d33
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Manual fixes for new cell connections API
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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b7dda72302
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
Clifford Wolf
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2bec47a404
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Use only module->addCell() and module->remove() to create and delete cells
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2014-07-25 17:56:19 +02:00 |
Clifford Wolf
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4a6d234ec7
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SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands
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2014-07-22 23:11:36 +02:00 |
Clifford Wolf
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28b3fd05fa
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
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2014-07-22 20:58:44 +02:00 |
Clifford Wolf
|
4b4048bc5f
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SigSpec refactoring: using the accessor functions everywhere
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
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SigSpec refactoring: renamed chunks and width to __chunks and __width
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
06d96e8fcf
|
Fixes in fsm detect/extract for better detection of non-fsm circuits
|
2013-12-06 12:53:20 +01:00 |
Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
Clifford Wolf
|
05483619f0
|
Some fixes to improve determinism
|
2013-08-09 12:42:32 +02:00 |
Clifford Wolf
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d97782b848
|
Sort ctrl signals in fsm_extract
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2013-08-08 15:46:00 +02:00 |
Clifford Wolf
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c32b918681
|
Renamed opt_rmunused to opt_clean
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2013-06-05 07:07:31 +02:00 |
Clifford Wolf
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10956cb84a
|
Added [[CITE]] tags to abc and fsm_extract passes
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2013-03-15 10:23:02 +01:00 |
Clifford Wolf
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a338d1a082
|
Added help messages for fsm_* passes
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2013-03-01 12:35:12 +01:00 |
Clifford Wolf
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a7988c01af
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Copy attributes from state signal to fsm cell
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2013-01-05 11:44:47 +01:00 |
Clifford Wolf
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7764d0ba1d
|
initial import
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2013-01-05 11:13:26 +01:00 |