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yosys
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3 Commits

Author SHA1 Message Date
Miodrag Milanovic b659082e4a hierarchy - proc reorder 2019-10-18 09:13:06 +02:00
Miodrag Milanovic c0fa6f3e1a Split mux tests per type 2019-10-04 13:05:16 +02:00
SergeyDegtyar 1070f2e90b Add new tests for Efinix architecture. 
Problems/questions:
	- fsm.ys. equiv_opt -assert failed because of unproven cells;
	- latches.ys,tribuf.ys - internal cells present;
	- memory.ys - sat called with -verify and proof did fail.
 2019-09-23 15:51:41 +03:00