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1056 Commits

Author SHA1 Message Date
Clifford Wolf edf11c635a Assert on new logic loops in "share" pass 2014-09-21 12:57:33 +02:00
Clifford Wolf a7758ef953 Added "test_abcloop" command 2014-09-19 15:51:34 +02:00
Clifford Wolf 5827826098 Small improvements in "abc" command handle_loops() function 2014-09-19 14:05:41 +02:00
Clifford Wolf 3aa003c8e9 Using "NOT" instead of "INV" as cell name in default abc genlib file 2014-09-19 13:15:31 +02:00
Clifford Wolf f7bb8f244b Alphabetically sort port names in "show" output 2014-09-19 11:13:10 +02:00
Clifford Wolf f56b92818b Do not run "scorr" in "abc -fast" 2014-09-18 19:00:21 +02:00
Clifford Wolf 815fab9d71 Added "abc -fast" 2014-09-18 12:57:37 +02:00
Clifford Wolf 9ae559b990 Fixed $_NOR vs. $_NOR_ typo in abc.cc 2014-09-16 12:45:05 +02:00
Clifford Wolf ae02d9cb9a Fixed $memwr/$memrd order in memory_dff 2014-09-16 12:40:58 +02:00
Clifford Wolf b86410b2ab More aggressive $macc merging in alumacc 2014-09-15 12:42:11 +02:00
Clifford Wolf b470c480e9 Added the obvious optimizations to alumacc $macc generator 2014-09-15 12:22:03 +02:00
Clifford Wolf fcbda07411 Improved maccmap tree bit packing 2014-09-15 12:00:19 +02:00
Clifford Wolf 2cbdbaad1f Fixed wreduce $shiftx handling 2014-09-15 11:29:09 +02:00
Clifford Wolf 7e156a5419 Fixed techmap_wrap for techmap_celltype 2014-09-14 15:34:36 +02:00
Clifford Wolf 014bb34e0e Various fixes/cleanups in alumacc and maccmap 2014-09-14 14:49:53 +02:00
Clifford Wolf 124e759280 Added techmap_wrap attribute 2014-09-14 14:49:26 +02:00
Clifford Wolf b34ca15185 alumacc fix for $pos cells 2014-09-14 14:00:14 +02:00
Clifford Wolf 0df1d9ad72 Extract $alu cells in alumacc 2014-09-14 13:23:44 +02:00
Clifford Wolf 7b16c63101 Merge $macc cells in alumacc pass 2014-09-14 11:21:37 +02:00
Clifford Wolf 0b72f0acb1 Basic $macc extract in alumacc 2014-09-14 10:45:28 +02:00
Clifford Wolf ff157fb74f alumacc skeleton 2014-09-14 10:02:00 +02:00
Clifford Wolf aab0e3bf70 Cleanup in wreduce 2014-09-14 10:01:30 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf 1a88e47396 Trim msb/lsb zero bits from full adder in maccmap 2014-09-08 11:21:58 +02:00
Clifford Wolf 6747a7047e Added "test_cell -const" 2014-09-08 11:12:39 +02:00
Clifford Wolf c50b841b29 Added 'techmap_maccmap' techmap attribute 2014-09-07 18:23:37 +02:00
Clifford Wolf 015dcdc84c Added "maccmap" command 2014-09-07 18:23:04 +02:00
Clifford Wolf 15b3c54fea Added "test_cell -nosat" 2014-09-07 17:05:41 +02:00
Clifford Wolf 9329a76818 Various bug fixes (related to $macc model testing) 2014-09-06 20:30:46 +02:00
Clifford Wolf fa64942018 Added $macc SAT model 2014-09-06 19:44:11 +02:00
Clifford Wolf b847ec8a0b Added $macc cell type 2014-09-06 15:47:46 +02:00
Clifford Wolf 34af6a1303 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-09-06 11:46:44 +02:00
Clifford Wolf e1743b3bac Added "test_cell -script" 2014-09-06 11:46:07 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf f5a40e7043 Fixed "opt_const -fine" for $pos cells 2014-09-04 08:55:58 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf 5733f4a39d Fixed "test_cells -vlog" 2014-09-03 13:43:37 +02:00
Clifford Wolf f1869667ca Improvements in "test_cell -vlog" 2014-09-02 23:21:15 +02:00
Clifford Wolf 66bf2bb92e Added test_cell -vlog 2014-09-02 22:49:43 +02:00
Clifford Wolf acd7a99aef Added SAT testing to test_cell eval stage 2014-09-02 17:28:13 +02:00
Clifford Wolf 37fe7c7bdf Removed references to yosys-svgviewer from docs 2014-09-02 04:03:06 +02:00
Clifford Wolf 9f00a0cd2d Using "xdot" instead of "yosys-svgviewer" in show command 2014-09-02 03:28:46 +02:00
Clifford Wolf 630befdf6d Added $alu support to test_cell 2014-09-01 16:36:04 +02:00
Clifford Wolf c7f81e4e49 Added "test_cell -simlib -v" 2014-09-01 15:37:21 +02:00
Clifford Wolf 826fdb34d8 Added "techmap -autoproc" 2014-09-01 15:36:29 +02:00
Clifford Wolf 27a1bfbec6 Fixes in old SAT example.ys 2014-09-01 11:45:47 +02:00
Clifford Wolf d5148f2e01 Moved "share" and "wreduce" to passes/opt/ 2014-09-01 11:45:26 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf e3664066d5 Added eval testing to test_cell 2014-08-31 18:08:42 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf 6ff46323a3 Improved write address decoder generation memory_map 2014-08-30 18:18:15 +02:00
Clifford Wolf 66763fad4e Using worker class in memory_map 2014-08-30 17:39:08 +02:00
Clifford Wolf 3a7d5d188d Don't change existing binary FSM encoding if it is already optimal 2014-08-30 14:43:06 +02:00
Clifford Wolf f910481f35 Using $pmux info in fsm_extract to optimize transition ctrl_in patterns 2014-08-30 14:34:49 +02:00
Clifford Wolf ab019b0bd5 Improved handling of $pmux cells in fsm_extract 2014-08-30 14:11:57 +02:00
Clifford Wolf d148b0af0d Fixed inserting of Q-inverters in dfflibmap 2014-08-27 19:44:12 +02:00
Clifford Wolf 084685f480 Implemented "rename -enumerate -pattern" 2014-08-26 12:51:08 +02:00
Clifford Wolf 7bbbe3580d Optimize shift ops with constant rhs in opt_const 2014-08-24 17:08:43 +02:00
Clifford Wolf 641501203c Added some additional log messages to opt_const 2014-08-24 17:08:43 +02:00
Clifford Wolf 9c5a63c52c azonenberg: Make dump_vcd save model when temporal induction fails due to step limit 2014-08-24 13:27:40 +02:00
Clifford Wolf c642dd0b3e Only call proc_share_dirname() in techmap when necessary 2014-08-23 15:32:00 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf fff12c719f Added "stat -width" 2014-08-22 17:20:28 +02:00
Clifford Wolf 98442e019d Added emscripten (emcc) support to build system and some build fixes 2014-08-22 16:20:22 +02:00
Clifford Wolf a3494fa9ed Added "plugin" command 2014-08-22 14:00:11 +02:00
Clifford Wolf 410d043dd8 Renamed toposort.h to utils.h 2014-08-17 00:55:35 +02:00
Clifford Wolf 7f734ecc09 Added module->uniquify() 2014-08-16 23:50:36 +02:00
Clifford Wolf 3b9157f9a6 Added "test_cell -s <seed>" 2014-08-16 19:44:31 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf eb17fbade5 Added "opt -fast" 2014-08-16 15:34:15 +02:00
Clifford Wolf 674f421b47 Bugfix in iopadmap 2014-08-15 14:29:42 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00
Clifford Wolf d320e75087 document "techmap -map %<design-name>" 2014-08-15 02:01:30 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf 28cf48e31f Some improvements in FSM mapping and recoding 2014-08-14 11:22:45 +02:00
Clifford Wolf 996c06f64d Added "abc -D" for setting delay target 2014-08-14 11:05:25 +02:00
Clifford Wolf 28bc7aeb93 Filter ANSI escape sequences from ABC output 2014-08-13 13:40:29 +02:00
Clifford Wolf 9d353fc543 Fixed handling of constant-true branches in proc_clean 2014-08-12 17:35:22 +02:00
Clifford Wolf 788bd02f97 Fixed FSM mapping for multiple reset-like signals 2014-08-10 12:04:02 +02:00
Clifford Wolf 9d4362990f Fixed "share" for complex scenarios with never-active cells 2014-08-09 17:07:20 +02:00
Clifford Wolf b9811d5aff Do not share any $reduce_* cells (its complicated and not worth it anyways) 2014-08-09 15:40:25 +02:00
Clifford Wolf 2faef89738 Some improvements in fsm_opt and fsm_map for FSM with unreachable states 2014-08-09 14:49:51 +02:00
Clifford Wolf 58ac605470 Another fsm_extract bugfix 2014-08-08 14:56:04 +02:00
Clifford Wolf 7067c43ec0 Fixed "fsm -export" 2014-08-08 14:56:03 +02:00
Clifford Wolf cb6ca08a53 Fixed sharing of reduce operator 2014-08-08 14:24:09 +02:00
Clifford Wolf 7c94024fc3 Fixed fsm_extract for wreduced muxes 2014-08-08 13:47:20 +02:00
Clifford Wolf 622ebab671 Added "sat -prove-skip" 2014-08-08 13:11:54 +02:00
Clifford Wolf 0b8b8d41eb Fixed build with gcc-4.6 2014-08-07 22:37:01 +02:00
Clifford Wolf c55eb8f8a6 Use "-keepdc" in "miter -equiv -flatten" 2014-08-07 16:42:35 +02:00
Clifford Wolf b4f10e342c Various improvements in memory_dff pass 2014-08-06 14:31:38 +02:00
Clifford Wolf 2501abe1ee Various fixes and improvements in wreduce pass 2014-08-05 19:01:41 +02:00
Clifford Wolf 5b3dc07b9a Removed old "constmap" from wreduce code 2014-08-05 16:53:53 +02:00
Clifford Wolf 523df73145 Added support for truncating of wires to wreduce pass 2014-08-05 14:47:03 +02:00
Clifford Wolf d3b1a29708 Cleanups and improvements in wreduce pass 2014-08-05 13:11:04 +02:00
Clifford Wolf 1c182cedb7 Added mux support to wreduce command 2014-08-05 12:49:53 +02:00
Clifford Wolf 0bb6942218 Added "show -signed" 2014-08-04 15:40:08 +02:00
Clifford Wolf ebbbe7fc83 Added RTLIL::IdString::in(...) 2014-08-04 15:40:07 +02:00
Clifford Wolf c7f99be3be Fixed "share" for memory read ports 2014-08-03 20:22:33 +02:00
Clifford Wolf 027376515a Progress in "wreduce" pass 2014-08-03 20:02:42 +02:00
Clifford Wolf 0b02f6ca30 Added "wreduce" command (work in progress) 2014-08-03 15:02:05 +02:00
Clifford Wolf 014a41fcf3 Implemented recursive techmap 2014-08-03 12:40:43 +02:00
Clifford Wolf 9bb5298c10 Fixes in show command (related to new IdString) 2014-08-03 12:40:23 +02:00
Clifford Wolf 08ec33a5e5 Implemented simplemap support for "techmap -extern" 2014-08-02 21:55:13 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 8e7361f128 Removed at() method from RTLIL::IdString 2014-08-02 19:08:02 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf 8fd1c269ac Fixed a performance bug in opt_reduce 2014-08-02 15:12:16 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf 03ef9a75c6 Added "test_autotb -n <num_iter>" option 2014-08-01 03:55:51 +02:00
Clifford Wolf 32a1cc3efd Renamed modwalker.h to modtools.h 2014-07-31 23:30:18 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf b5a9e51b96 Added "trace" command 2014-07-31 15:02:16 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 6ca0c569d9 Added "techmap -assert" 2014-07-31 02:21:41 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf 6400ae3648 Added write_file command 2014-07-30 19:59:29 +02:00
Clifford Wolf ceecf5b153 Improvements in test_cell 2014-07-30 18:49:12 +02:00
Clifford Wolf 273383692a Added "test_cell" command 2014-07-29 22:07:41 +02:00
Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf 77e2d39cd0 Allow "hierarchy -generate" for $__ cells 2014-07-29 16:35:13 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 8b0f50792c Added techmap -extern 2014-07-27 21:31:18 +02:00
Clifford Wolf 5da343b7de Added topological sorting to techmap 2014-07-27 16:43:39 +02:00
Clifford Wolf 0c86d6106c Added SigPool::check(bit) 2014-07-27 15:38:02 +02:00
Clifford Wolf 77a1462f2d Fixed bug in opt_clean 2014-07-27 15:13:29 +02:00
Clifford Wolf d07a871d35 Improved performance of opt_const on large modules 2014-07-27 14:50:25 +02:00
Clifford Wolf dbb3556e3f Fixed a bug in opt_clean and some RTLIL API usage cleanups 2014-07-27 13:19:05 +02:00
Clifford Wolf d878fcbdc7 Added log_cmd_error_expection 2014-07-27 12:05:50 +02:00
Clifford Wolf 49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf 5826670009 Various RTLIL::SigSpec related code cleanups 2014-07-25 14:25:42 +02:00
Clifford Wolf 0520bfea89 Fixed memory corruption in "opt_reduce" pass 2014-07-25 12:49:51 +02:00
Clifford Wolf c4e4f79a2a Disabled cover() for non-linux builds 2014-07-25 12:27:36 +02:00
Clifford Wolf 91bf0c90c8 Improvements in "cover" command 2014-07-25 12:04:40 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf 9962384d3e Added cover() calls to opt_const 2014-07-24 20:47:18 +02:00
Clifford Wolf 45b4154b37 Added "make SMALL=1" 2014-07-24 19:03:57 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf 2f54345cff Added "cover" command 2014-07-24 16:14:19 +02:00
Clifford Wolf 20a7965f61 Various small fixes (from gcc compiler warnings) 2014-07-23 20:45:27 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 2014-07-23 09:34:47 +02:00
Clifford Wolf 4a6d234ec7 SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands 2014-07-22 23:11:36 +02:00
Clifford Wolf 65a939cb27 Fixed memory corruption with new SigSpec API in proc_mux 2014-07-22 22:54:39 +02:00
Clifford Wolf e7e30f1c86 fixed memory leak in fsm_opt 2014-07-22 22:52:57 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 137dbf3cf7 Added "opt_const -keepdc" 2014-07-21 21:38:55 +02:00
Clifford Wolf 1873480ca5 Added mul to mux conversion to "opt_const -fine" 2014-07-21 17:19:50 +02:00
Clifford Wolf 1241a9fd50 Added "opt_const -fine" and "opt_reduce -fine" 2014-07-21 16:34:16 +02:00
Clifford Wolf e035f1d886 Added opt_const support for simple identities 2014-07-21 14:41:02 +02:00
Clifford Wolf 361e0d62ff Replaced depricated NEW_WIRE macro with module->addWire() calls 2014-07-21 12:42:02 +02:00
Clifford Wolf 1d88f1cf9f Removed deprecated module->new_wire() 2014-07-21 12:35:06 +02:00
Clifford Wolf 3cb61d03f8 Wider range of cell types supported in "share" pass 2014-07-21 12:18:29 +02:00
Clifford Wolf b49beab1f3 Use ezSAT::non_incremental() in "share" pass 2014-07-21 02:08:38 +02:00
Clifford Wolf 04fcb07213 Added support for resource sharing in mux control logic 2014-07-20 20:44:14 +02:00
Clifford Wolf 1ce5e83555 Added "select -assert-count" 2014-07-20 20:15:49 +02:00
Clifford Wolf e9506bb2da Supercell creation for $div/$mod worked all along, fixed test benches 2014-07-20 18:54:06 +02:00
Clifford Wolf ff28029fdb Fixed creation of shift supercells in "share" pass 2014-07-20 17:06:36 +02:00
Clifford Wolf 4c38ec1cc8 Added "miter -equiv -flatten" 2014-07-20 15:33:07 +02:00
Clifford Wolf 8d04ca7d22 Added call_on_selection() and call_on_module() API 2014-07-20 15:33:06 +02:00
Clifford Wolf 5b3ee7a072 Added "share" supercell creation 2014-07-20 15:01:17 +02:00
Clifford Wolf 7b98e46ac3 Added removing of always inactive cells to "share" pass 2014-07-20 13:24:36 +02:00
Clifford Wolf 8819493db4 Progress in "share" pass 2014-07-20 11:04:52 +02:00
Clifford Wolf 15fd615da5 Progress in "share" pass 2014-07-20 03:03:04 +02:00
Clifford Wolf 2278995bd8 Started to implement real resource sharing 2014-07-19 20:54:32 +02:00
Clifford Wolf efd9604dfb Improved memory_share log messages 2014-07-19 15:46:11 +02:00
Clifford Wolf e0a819dbe5 More verbose memory_share help message 2014-07-19 15:34:14 +02:00
Clifford Wolf 297a0962ea Added SAT-based write-port sharing to memory_share 2014-07-19 15:33:55 +02:00
Clifford Wolf 26f982ac0b Fixed bug in memory_share feedback-to-en code 2014-07-19 15:32:14 +02:00
Clifford Wolf e441f07d89 Added translation from read-feedback to en-signals in memory_share 2014-07-18 16:46:40 +02:00
Clifford Wolf 44f13aff92 Improved seeding of color rng in show command 2014-07-18 16:44:45 +02:00
Clifford Wolf a341931972 Only create collision detect logic in memory_share if necessary 2014-07-18 14:32:40 +02:00
Clifford Wolf ab4b26679f Added memory_share 2014-07-18 13:16:56 +02:00
Clifford Wolf 309ae98246 Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port 2014-07-18 10:28:45 +02:00
Clifford Wolf 1b00861d0a Improved opt_reduce handling of mem wr_en mux bits 2014-07-17 12:12:04 +02:00
Clifford Wolf b76bf05cda Added support for "blackbox" attribute to iopadmap 2014-07-17 08:59:07 +02:00
Clifford Wolf 64a6906cc4 Added support for "blackbox" attribute to flatten/techmap 2014-07-17 08:58:51 +02:00
Clifford Wolf d678b6533d improved opt_reduce for $mem/$memwr WR_EN multiplexers 2014-07-16 14:08:51 +02:00
Clifford Wolf 765f172211 Changes to "memory" pass for new $memwr/$mem WR_EN interface 2014-07-16 12:49:50 +02:00
Clifford Wolf 3b52121d32 now ignore init attributes on non-register wires in sat command 2014-07-05 11:18:38 +02:00
Clifford Wolf 1c85584fe5 Do not create $dffsr cells with no-op resets in proc_dff 2014-06-19 12:29:29 +02:00
Clifford Wolf 22a998903b Added %D and %c select commands 2014-06-14 16:19:32 +02:00
Clifford Wolf 744e518467 fixed cell array handling of positional arguments 2014-06-07 12:17:11 +02:00
Clifford Wolf e275e8eef9 Add support for cell arrays 2014-06-07 11:48:50 +02:00
Clifford Wolf 7020f7fc13 added tee cmd 2014-06-03 09:23:31 +02:00
Clifford Wolf 68c99bf734 Fixed log messages in memory_dff 2014-06-01 11:32:27 +02:00
Johann Glaser 278085fa01 added log_header to miter and expose pass, show cell type for exposed ports 2014-05-28 18:05:38 +02:00
Johann Glaser 684c85902d be more verbose when techmap yielded processes 2014-05-26 17:13:41 +02:00
Clifford Wolf 68c059565a Fixed bug in opt_reduce (see vloghammer issue_044) 2014-05-12 12:45:47 +02:00
Clifford Wolf f69b5800c9 fixed syntax error in dot file created by "show" command 2014-05-10 16:22:56 +02:00
Clifford Wolf 9a34486bfb Fixed performance problem in opt_mux with nets driven by many conflicting drivers 2014-03-19 10:05:01 +01:00
Clifford Wolf 34e54cda5b Small improvement in SAT log messages 2014-03-13 13:12:49 +01:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Siesh1oo 8127d5e8c3 - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). 
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
 - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
 2014-03-12 23:17:14 +01:00
Clifford Wolf 9087ece97c OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:52:37 +01:00
Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf fa75c8286e Fixed memory corruption in passes/abc/blifparse.cc 2014-03-11 13:09:01 +01:00
Clifford Wolf fcae92868d Fixed dumping of timing() { .. } block in libparse 2014-03-09 15:16:07 +01:00
Clifford Wolf 22aabe05c9 Verbose reading of liberty and constr files in ABC pass 2014-03-09 15:15:38 +01:00
Clifford Wolf e3b11ea2d6 Fixed bug in freduce command 2014-03-07 18:44:23 +01:00
Clifford Wolf 6f8865d81a Some minor code cleanups in freduce command 2014-03-07 18:29:04 +01:00
Clifford Wolf 54d74cf616 Added freduce -dump 2014-03-06 22:06:58 +01:00
Clifford Wolf da5859a674 Added freduce -stop 2014-03-06 18:14:26 +01:00
Clifford Wolf 9b9c3327cc Fixed undef handling in opt_reduce 2014-03-06 14:18:34 +01:00
Clifford Wolf 1ecaf1bb76 Added techmap -max_iter option 2014-03-06 12:15:17 +01:00
Clifford Wolf 96e753041d fixed freduce for Minisat::SimpSolver: use frozen_literal() 2014-03-03 02:14:27 +01:00
Clifford Wolf 9e99984336 Fixed const folding of $bu0 cells 2014-02-27 04:09:32 +01:00
Clifford Wolf 548519875b Fixed bug (typo) in passes/opt/opt_const.cc 2014-02-22 17:07:22 +01:00
Clifford Wolf 8b508dc90b Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst 2014-02-21 23:34:45 +01:00
Clifford Wolf 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap 2014-02-20 23:42:07 +01:00
Clifford Wolf 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." 2014-02-20 23:31:13 +01:00
Clifford Wolf 236fc4209c Added "extract -map %<design_name>" 2014-02-20 23:30:15 +01:00
Clifford Wolf 483c99fe46 Added "design -push" and "design -pop" 2014-02-20 23:28:59 +01:00
Clifford Wolf 0dadfed46d Added connwrappers command 2014-02-20 20:44:11 +01:00
Clifford Wolf 23a3b488a0 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-18 20:05:53 +01:00
Clifford Wolf a71d09421d Added techmap support for _TECHMAP_CONNMAP_*_ 2014-02-18 19:51:00 +01:00
Clifford Wolf a78bba1f5c Added "sat -dump_cnf" 2014-02-18 09:29:08 +01:00
Clifford Wolf 32af10fa9b Coding style corrections in SatHelper::dump_model_to_vcd() 2014-02-18 09:28:05 +01:00
Clifford Wolf 13051e6acf Added "sat -initsteps" 2014-02-18 09:03:16 +01:00
Clifford Wolf 0851c2b6ea Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups 2014-02-17 13:59:39 +01:00
Andrew Zonenberg 4a948d780a Added "-dump_fail_to_vcd" argument to SAT solver 2014-02-17 13:52:36 +01:00
Clifford Wolf ca53ef5098 Better preserve wires when flattening (in comparison to techmap) 2014-02-17 09:44:39 +01:00
Clifford Wolf 6d63f39eb6 Added some additional checks to techmap 2014-02-16 22:18:06 +01:00
Clifford Wolf a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap 2014-02-16 21:58:59 +01:00
Clifford Wolf 28e14ee50a Fixed handling of "keep" attribute on wires in opt_clean 2014-02-16 21:58:27 +01:00
Clifford Wolf 42ce3db983 Fixed use of selection in splitnets command 2014-02-16 17:39:50 +01:00
Clifford Wolf d3dc22a90f Added recursion support to techmap 2014-02-16 17:16:44 +01:00
Clifford Wolf 9a816b65a8 Added != support for relational select pattern 2014-02-16 00:16:54 +01:00
Clifford Wolf 623a68f528 Added iopadmap -bits 2014-02-15 21:59:26 +01:00
Clifford Wolf cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff 2014-02-15 16:34:12 +01:00
Clifford Wolf 67effc9f5b Fixed opt_const handling of double invert with non-1 output width 2014-02-15 13:16:08 +01:00
Clifford Wolf 3121d19d95 Added abc -keepff option 2014-02-14 11:28:42 +01:00
Clifford Wolf de3ea9269a updated default ABC command strings 2014-02-13 19:14:15 +01:00
Clifford Wolf a123941618 Updated ABC 2014-02-13 18:56:36 +01:00
Clifford Wolf cd9e8741a7 Implemented read_verilog -defer 2014-02-13 13:59:13 +01:00
Clifford Wolf b463907890 Removed double blanks in ABC default command sequences 2014-02-13 08:12:52 +01:00
Clifford Wolf 7664f5d92b Updated ABC and some related changes 2014-02-13 08:07:08 +01:00
Clifford Wolf ab71bd0746 Updated ABC to rev e97a6e1d59b9 2014-02-12 08:35:42 +01:00
Clifford Wolf 38469e7686 Various improvements in expose command (added -sep and -cut) 2014-02-09 11:07:46 +01:00
Clifford Wolf b6f33576d5 Added delete {-input|-output|-port} 2014-02-09 10:03:26 +01:00
Clifford Wolf b3b5fac191 Bugfix in delete command 2014-02-09 09:34:58 +01:00
Clifford Wolf 85914c36e5 Fixed handling of async reset in expose -evert-dff 2014-02-08 21:26:40 +01:00
Clifford Wolf db86aaa07d Build fixes for log cmd 2014-02-08 21:21:51 +01:00
Clifford Wolf c06de50f05 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-08 21:08:46 +01:00
Clifford Wolf 0935e20003 Implemented expose -evert-dff 2014-02-08 21:08:38 +01:00
Johann Glaser af14bb5f65 added "log" command 2014-02-08 19:19:32 +01:00
Clifford Wolf 7f52c18a22 Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect 2014-02-08 19:13:19 +01:00
Clifford Wolf 926fa61119 Added various new options to splice command 2014-02-08 16:37:18 +01:00
Clifford Wolf 0c11d04144 Added %a select operator 2014-02-08 16:31:38 +01:00
Clifford Wolf 6644f80d97 Moved some passes to other source directories 2014-02-08 14:39:15 +01:00
Clifford Wolf 03ee63ff80 Added support for "keep" attribute to abc pass 2014-02-08 14:25:29 +01:00
Clifford Wolf 82c98bbbe6 Added opt -purge (frontend to opt_clean -purge) 2014-02-08 14:21:34 +01:00
Clifford Wolf 922d1c9520 Only count non-trivial attributes when findinf master signal in opt_clean 2014-02-08 14:21:04 +01:00
Clifford Wolf 2c51619c2b Now also move net labes to the right position in splice cmd 2014-02-08 00:06:00 +01:00
Clifford Wolf 274bcef66c Improved detection of primary wire for a signal in opt_clean 2014-02-07 23:50:17 +01:00
Clifford Wolf 244e8ce1f4 Added splice command 2014-02-07 20:30:56 +01:00
Clifford Wolf 08aa1062b4 Added log_header() to splitnets 2014-02-07 19:51:15 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf 99b1e9ee56 Re-enabled abc "retime" after sorting yout the yosys-bigsim problem 2014-02-07 16:36:37 +01:00
Clifford Wolf 366dcd3abf Fixed use of "cmd_error" in passes/cmds/design.cc 2014-02-07 14:16:42 +01:00
Clifford Wolf 0192f1c66e Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed) 2014-02-06 22:31:58 +01:00
Clifford Wolf 58cb8d65af Added "retime" to standard ABC recipes 2014-02-06 22:16:20 +01:00
Clifford Wolf 91eab69912 Added copy command 2014-02-06 22:09:21 +01:00
Clifford Wolf cf593222f2 Added design -stash/-copy-from/-copy-to 2014-02-06 21:52:07 +01:00
Clifford Wolf 37fdb2ca7a Added support for s: select expressions (wire width) 2014-02-06 19:45:03 +01:00
Clifford Wolf 9428050dd6 Added i:, o:, and x: selection pattern 2014-02-06 19:35:33 +01:00
Clifford Wolf d7d1c7baf8 Added support for %m selection op 2014-02-06 19:30:08 +01:00
Clifford Wolf f2fdcef13d Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-06 19:22:50 +01:00
Clifford Wolf fa295a4528 Added generic RTLIL::SigSpec::parse_sel() with support for selection variables 2014-02-06 19:22:46 +01:00
Johann Glaser 34eb77d2bf new %s: add sub-modules to selection 2014-02-06 17:36:39 +01:00
Clifford Wolf d4b0f28881 Added support for sat -show @<sel_name> 2014-02-06 17:32:51 +01:00
Clifford Wolf b1a12c5f37 Added sat -set-init-def and sat -tempinduct-def 2014-02-06 16:15:23 +01:00
Clifford Wolf 594d52e0b6 Added opt_const -undriven 2014-02-06 15:49:03 +01:00
Clifford Wolf c526e56747 Added expose -dff 2014-02-06 15:48:42 +01:00
Clifford Wolf c13c5b9b7b Changed techmap description from "simple" to "generic" 2014-02-06 13:10:06 +01:00
Clifford Wolf eb8fd4a163 Added miter -make_outcmp 2014-02-06 02:20:55 +01:00
Clifford Wolf 80a1cdb0e2 Added sat -set-init-zero support 2014-02-06 01:40:01 +01:00
Clifford Wolf e915043144 Added sat -verify and -falsify support for non-prove cases 2014-02-06 00:59:41 +01:00
Clifford Wolf cd06055e77 Added expose command 2014-02-05 23:59:55 +01:00
Clifford Wolf dbfcc2f4e2 Simplified select "Assertation failed" message generation 2014-02-05 18:52:55 +01:00
Clifford Wolf 94b802c65d Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-05 18:46:47 +01:00
Clifford Wolf f6e6e9b844 Added selection support for r: and selection with relational operators 2014-02-05 18:24:45 +01:00
Johann Glaser 3c0b5139a1 be more verbose for select -assert-any and -assert-none 2014-02-05 16:03:02 +01:00
Johann Glaser 667543de0b improved help for "select" 2014-02-05 15:53:02 +01:00
Clifford Wolf 5bf33de24a Added setattr and setparam commands 2014-02-05 11:11:55 +01:00
Clifford Wolf 1fb8ba73bd Throw errors if non-existing selection variables are used 2014-02-04 23:31:06 +01:00
Clifford Wolf b1bf55dd63 Added select -none 2014-02-04 23:23:44 +01:00
Clifford Wolf 99b9c56da1 Fixed detection of init attribute in opt_rmdff 2014-02-04 23:00:32 +01:00
Clifford Wolf 69e867f3e8 Added support for inline commands to abc -script 2014-02-04 22:01:53 +01:00
Clifford Wolf 7a5f378bae Added hierarchy -purge_lib option 2014-02-04 16:50:13 +01:00
Clifford Wolf 6891fd79a3 added sat -falsify 2014-02-04 13:34:37 +01:00
Clifford Wolf d267bcde4e Fixed bug in sequential sat proofs and improved handling of asserts 2014-02-04 12:46:16 +01:00
Clifford Wolf ecdf1f5577 Improved handling of reg init in opt_share and opt_rmdff 2014-02-04 12:02:47 +01:00
Clifford Wolf 9e35021585 Addred sat option -ignore_unknown_cells 2014-02-03 16:26:10 +01:00
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf de336d93b2 More opt_const -mux_bool features 2014-02-02 22:41:24 +01:00
Clifford Wolf 9d0b69edaa Added opt_const -mux_bool 2014-02-02 22:11:08 +01:00
Clifford Wolf bee4450c4c Added support for inverter chains to opt_const 2014-02-02 21:46:42 +01:00
Clifford Wolf 67b0ce2578 Only generate write-enable $and if WE is not constant 1 in memory_map 2014-02-02 21:27:26 +01:00
Clifford Wolf 83fa652820 Added constant-clock case to opt_rmdff 2014-02-02 21:09:08 +01:00
Clifford Wolf aa732b0c73 Added show -notitle option 2014-02-02 17:55:32 +01:00
Clifford Wolf 9808acdc75 Added delete command 2014-02-02 17:11:19 +01:00
Clifford Wolf a9e2d86f86 Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax 2014-02-02 16:47:17 +01:00
Clifford Wolf f4f0bd6eef Fixed a bug in miter command 2014-02-01 22:53:27 +01:00
Clifford Wolf 374674aff4 Added sat -show-inputs and -show-outputs 2014-02-01 22:52:44 +01:00
Clifford Wolf caf540d1ad Added show -color support for cells and finished show -label implementation 2014-02-01 18:23:32 +01:00
Clifford Wolf fa92722358 Added miter command 2014-02-01 10:35:56 +01:00
Johann Glaser e9a2094774 enabled multiple "-map" for the extract pass 2014-01-25 21:11:34 +01:00
Clifford Wolf c1ed2607fb Added support for // comments in liberty parser 2014-01-25 06:32:16 +01:00
Clifford Wolf 32a91458a7 Added hilomap command 2014-01-19 21:58:58 +01:00
Clifford Wolf 03a876c7e8 Added sat -tempinduc and sat -prove-asserts 2014-01-19 16:35:17 +01:00
Clifford Wolf 1e67099b77 Added $assert cell 2014-01-19 14:03:40 +01:00
Clifford Wolf 839af272ad Improved setundef random number generator 2014-01-18 02:56:36 +01:00
Clifford Wolf 091d9abc3e Added setundef command 2014-01-17 23:14:36 +01:00
Clifford Wolf 2e370d5a2f Added support for $adff with undef data inputs to opt_rmdff 2014-01-17 16:42:40 +01:00
Clifford Wolf 651ce67d97 Added select -assert-none and -assert-any 2014-01-17 16:34:50 +01:00
Clifford Wolf f3154f5694 Added automatic memid generation to memory_unpack command 2014-01-17 00:15:15 +01:00
Clifford Wolf 4d8318ad1b Added memory_unpack command 2014-01-17 00:05:02 +01:00
Martin Schmölzer aa17f16fec Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3)) 
This fixes compilation errors on Arch Linux.

Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
 2014-01-14 20:12:45 +01:00
Clifford Wolf 0c5b1f32d4 Added hierarchy -libdir option 2014-01-14 19:28:20 +01:00
Clifford Wolf 9a00980129 renamed LibertyParer to LibertyParser 2014-01-14 18:57:47 +01:00
Clifford Wolf c1da7661a5 Added "+" to list of liberty token characters 2014-01-14 18:56:29 +01:00
Clifford Wolf 54275c61ee Added "opt_const -mux_undef" 2014-01-14 11:10:29 +01:00
Clifford Wolf bc541b47ea Improved performance of freduce input cone reduction 2014-01-04 13:10:51 +01:00
Clifford Wolf b791af174e Improved freduce performance on const signals 2014-01-04 00:06:36 +01:00
Clifford Wolf 10f45b8c8e Performance improvements in freduce pass 2014-01-03 21:29:28 +01:00
Clifford Wolf c44e1bec6d More freduce cleanups 2014-01-03 18:17:28 +01:00
Clifford Wolf 03f0ab9de2 Cleanups in freduce command 2014-01-03 17:50:39 +01:00
Clifford Wolf 8a8d444648 Tiny cleanup in proc_mux.cc 2014-01-03 16:54:59 +01:00
Clifford Wolf 60fbca9970 Added "splitnets -driver" 2014-01-03 14:01:06 +01:00
Clifford Wolf bf5e5429c1 Use selection in freduce command 2014-01-03 13:15:11 +01:00
Clifford Wolf c3e9f0712f Another small freduce cleanup/bugfix 2014-01-03 12:34:18 +01:00
Clifford Wolf 914e208aa3 Added "connect" command 2014-01-03 12:33:00 +01:00
Clifford Wolf 67d155078d More freduce cleanups and bugfixes 2014-01-03 02:44:05 +01:00
Clifford Wolf fb2bf934dc Added correct handling of $memwr priority 2014-01-03 00:22:17 +01:00
Clifford Wolf 536e20bde1 Fixed more complex undef cases in freduce 2014-01-02 23:40:20 +01:00
Clifford Wolf 5a0f561d9c Now */ is optional in */<mode>:<arg> selections 2014-01-02 20:35:37 +01:00
Clifford Wolf 456ae31a8a Added "rename -hide" command 2014-01-02 20:23:34 +01:00
Clifford Wolf 0759c97748 More "freduce" related fixes and improvements 2014-01-02 19:37:34 +01:00
Clifford Wolf ced4d7b321 Added support for module->connections to select %ci, %co and %x handling 2014-01-02 18:44:24 +01:00
Clifford Wolf c6b33f81eb Some cleanups in freduce -inv mode (and switched from -noinv to -inv) 2014-01-02 18:11:01 +01:00
Clifford Wolf 249ef8695a Major rewrite of "freduce" command 2014-01-02 16:52:33 +01:00
Clifford Wolf e09ebf475c Fixed use of limited length buffer in ABC blif parser 2013-12-31 21:58:35 +01:00
Clifford Wolf 4892a3ce6d Added abc -dff and -clk support 2013-12-31 21:25:09 +01:00
Clifford Wolf be5dab87fd Now using BLIF as ABC input format 2013-12-31 14:29:29 +01:00
Clifford Wolf c616802ac7 Always use BLIF as ABC output format 2013-12-31 13:41:16 +01:00
Clifford Wolf bf607df6d5 Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen) 2013-12-29 17:39:49 +01:00
Clifford Wolf fe8ec32a1c Added new cell types to manual 2013-12-28 12:10:32 +01:00
Clifford Wolf c69c416d28 Added $bu0 cell (for easy correct $eq/$ne mapping) 2013-12-28 12:02:14 +01:00
Clifford Wolf 7f71787599 Added sat -prove-x and -set-def-inputs 2013-12-28 11:24:36 +01:00
Clifford Wolf bd39263796 Improved $_MUX_ handling in opt_const 2013-12-28 10:30:31 +01:00
Clifford Wolf d81e3ed3ae More conservastive $eq/$ne/$eqx/$nex opt_const code 2013-12-28 10:29:22 +01:00
Clifford Wolf c9699fe76d More $eq/$ne/$eqx/$nex fixes in opt_const 2013-12-27 15:18:14 +01:00
Clifford Wolf 7b02a44efb Fixed/improved opt_const $eq/$ne/$eqx/$nex handling 2013-12-27 14:21:24 +01:00
Clifford Wolf 369bf81a70 Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
Clifford Wolf 11ffa78677 Added sat -set-def/-set-*-undef support 2013-12-27 13:27:21 +01:00
Clifford Wolf fb31d10236 Renamed sat -set-undef to -set-any-undef 2013-12-27 13:02:46 +01:00
Clifford Wolf 334b0cc803 Fixed dfflibmap for unused output ports 2013-12-21 20:47:22 +01:00
Clifford Wolf 8856cec308 Now prefer smallest cells in dfflibmap 2013-12-21 08:42:37 +01:00
Clifford Wolf 1fb29050e5 Cleanup of dfflibmap cellmap exploration code 2013-12-20 14:21:18 +01:00
Clifford Wolf eaf7d9675d Further improved dfflibmap cellmap exploration 2013-12-20 12:34:34 +01:00
Clifford Wolf 404bcc2d1e Fixed dfflibmap endless-loop bug 2013-12-20 12:13:51 +01:00
Clifford Wolf c904f5e197 Prefer non-inverted clocks in dfflibmap 2013-12-19 13:21:57 +01:00
Clifford Wolf 2b90ba1e96 Added sat -max_undef feature 2013-12-07 23:58:55 +01:00
Clifford Wolf 8a815ac741 Added "sat" undef support and "sat -set-init" options 2013-12-07 17:28:51 +01:00
Clifford Wolf 5de57e9970 Fixed compiler warining in passes/sat/eval.cc 2013-12-07 16:19:24 +01:00
Clifford Wolf 325b764341 Added eval -set-undef and eval -table 2013-12-07 11:58:22 +01:00
Clifford Wolf 06d96e8fcf Fixes in fsm detect/extract for better detection of non-fsm circuits 2013-12-06 12:53:20 +01:00
Clifford Wolf f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf 6e227e3666 Fixed submod for non-primitive cells 2013-12-02 12:53:55 +01:00
Clifford Wolf e881878341 Fixed submod for non-cleaned designs 2013-12-02 12:18:07 +01:00
Clifford Wolf 97efc2ed5f A fix in memory_dff for write ports with static addresses 2013-12-01 14:08:18 +01:00
Clifford Wolf 7295b25955 Progress on AppNote 011 2013-11-29 16:42:49 +01:00
Clifford Wolf c60aaf8fa3 Added pattern support to "ls" command 2013-11-28 21:34:41 +01:00
Clifford Wolf 293356e87c Improved ID matching scheme in select (and thus for all commands) 2013-11-28 21:13:16 +01:00
Clifford Wolf 792bbad448 Fixes and improvements in "show" command 2013-11-28 21:02:19 +01:00
Clifford Wolf 0e52f3fa01 Added "src" attribute to processes 2013-11-28 17:37:50 +01:00
Clifford Wolf 5af7f4db72 Added support for "show -pause" and "show -format dot" 2013-11-28 13:35:28 +01:00
Clifford Wolf 38e7fa6530 Tighter integration of ABC build 2013-11-27 09:08:35 +01:00
Clifford Wolf bc3cc88719 Started implementing undef support in "sat" command 2013-11-25 21:40:00 +01:00
Clifford Wolf 3d95047ce2 Bugfixes in new "stat" command 2013-11-25 21:08:34 +01:00
Clifford Wolf 4c7d6e63ec Added "stat" command 2013-11-25 20:43:57 +01:00
Clifford Wolf 61412d167f Improvements in satgen undef handling 2013-11-25 16:50:45 +01:00
Clifford Wolf bd65e67d8a Improvements in satgen undef handling 2013-11-25 15:12:01 +01:00
Clifford Wolf 8c3f4b3957 Started implementing undef handling in satgen 2013-11-25 04:51:33 +01:00
Clifford Wolf 76f7c10cfc Using simplemap mappers from techmap 2013-11-24 23:31:14 +01:00
Clifford Wolf 3ee33cbdaf Added simplemap pass 2013-11-24 22:52:30 +01:00
Clifford Wolf 8dafecd34d Added module->avail_parameters (for advanced techmap features) 2013-11-24 20:29:07 +01:00
Clifford Wolf 4011d47646 Added techmap -D and -I options 2013-11-24 20:04:48 +01:00
Clifford Wolf 20175afd29 Added "techmap -share_map" option 2013-11-24 19:50:25 +01:00
Clifford Wolf f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
Clifford Wolf 609caa23b5 Implemented correct handling of signed module parameters 2013-11-24 17:17:21 +01:00
Clifford Wolf 72b35e0b99 Fixed "flatten" top-module detection: Only use on fully selected designs 2013-11-24 14:10:46 +01:00
Clifford Wolf 28093d9dd2 Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
Clifford Wolf 5f9c7fc6ea Improved handling of techmap special wires 2013-11-23 16:49:58 +01:00
Clifford Wolf 532091afcb Added more generic _TECHMAP_ wire mechanism to techmap pass 2013-11-23 15:58:06 +01:00
Clifford Wolf 295e352ba6 Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00
Clifford Wolf 1c4a6411af Updated abc 2013-11-21 22:39:10 +01:00
Clifford Wolf 09471846c5 Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
Clifford Wolf 84ced2bb8e Fixed a bug in "add -global_input" 2013-11-21 03:01:20 +01:00
Clifford Wolf 64a5f8f75e Added "proc_arst -global_arst" feature 2013-11-20 21:00:43 +01:00
Clifford Wolf 2279b2a196 Added "add" command (only wires for now) 2013-11-20 19:37:40 +01:00
Clifford Wolf 63285b300c Renamed temp module generated by "abc" pass from "logic" to "netlist" 2013-11-19 01:03:57 +01:00
Clifford Wolf a694324a75 Fixed abc pass blif parser for constant bits 2013-11-13 15:46:28 +01:00
Clifford Wolf e5b974fa2a Cleanups and bugfixes in response to new internal cell checker 2013-11-11 00:39:45 +01:00
Clifford Wolf 378cc509cd Call internal checker more often 2013-11-10 23:24:21 +01:00
Clifford Wolf 223892ac28 Improved user-friendliness of "sat" and "eval" expression parsing 2013-11-09 12:02:27 +01:00
Clifford Wolf 18f9477e95 Added verification of SAT model to "eval -vloghammer_report" command 2013-11-09 11:38:17 +01:00
Clifford Wolf b04051a0e2 Fixed keep attribute on wires in opt_clean 2013-11-08 05:20:15 +01:00
Clifford Wolf 947bd9b96b Renamed extend_un0() to extend_u0() and use it in genrtlil 2013-11-07 18:17:10 +01:00
Clifford Wolf 0e1661f84e Fixed type of sign extension in opt_const $eq/$ne handling 2013-11-07 16:53:28 +01:00
Clifford Wolf db42a8f89b Fixed $eq/$ne bitwise optimization in opt_const 2013-11-07 11:54:59 +01:00
Clifford Wolf f485962c5e Added handling of unconnected/unspecified signals to eval -vloghammer_report 2013-11-06 22:42:07 +01:00
Clifford Wolf 031a91dc94 Added correct RTL undef handling to eval vloghammer mode 2013-11-06 13:16:47 +01:00
Clifford Wolf f94266bb42 Added eval -vloghammer_report mode 2013-11-06 04:14:56 +01:00
Clifford Wolf 1d34fd7608 Added support for "keep" attributes on wires 2013-11-05 15:52:29 +01:00
Clifford Wolf eab536a203 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-11-03 21:13:21 +01:00
Clifford Wolf f7f0af6f9c Added resolution of positional arguments to hierarchy pass 2013-11-03 09:42:51 +01:00
Clifford Wolf 0efe16f118 Added placeholder check to dfflibmap and cleaned up some other placeholder checks 2013-10-31 12:27:07 +01:00
Clifford Wolf b8bfa020fa Added detection for endless recursion in fsm_detect pass 2013-10-30 00:47:58 +01:00
Clifford Wolf 888c43210b Fixed help message typo (memory pass) 2013-10-30 00:47:31 +01:00
Clifford Wolf 613750155d Added -format option to splitnets 2013-10-29 11:01:04 +01:00
Clifford Wolf ceb971eab9 Added support for i/o buffers to iopadmap 2013-10-26 22:27:40 +02:00
Clifford Wolf dd56004fc0 Added support for sr flip-flops to dfflibmap 2013-10-24 18:20:06 +02:00
Clifford Wolf 628b994cf6 Added support for complex set-reset flip-flops in proc_dff 2013-10-24 16:54:05 +02:00
Clifford Wolf e679a5d046 Fixed handling of boolean attributes (passes) 2013-10-24 11:37:54 +02:00
Clifford Wolf d61699843f Improved handling of dff with async resets 2013-10-21 14:51:58 +02:00
Clifford Wolf 56ea230676 Added handling of multiple async paths in proc_arst 2013-10-19 00:50:13 +02:00
Clifford Wolf bfa1a65fa9 Added dffsr support to proc_dff pass 2013-10-18 13:26:52 +02:00
Clifford Wolf 9bc703b964 Improved way of connecting ports in techmap pass 2013-10-17 22:19:38 +02:00
Clifford Wolf 8cc53ef72c Only prefer connected signals iff they have public names 2013-10-17 22:10:55 +02:00
Clifford Wolf 95dbacefbf Fixed bug in synthesis of memories that are never written 2013-10-17 21:00:37 +02:00
Clifford Wolf c20571ca5e Avoid re-arranging signals on register outputs 2013-10-17 20:48:40 +02:00
Clifford Wolf f5c0ed6c79 Fixed detection of major wires in opt_clean 2013-10-17 02:41:59 +02:00
Clifford Wolf 96e7abad48 Added iopadmap pass 2013-10-16 16:16:06 +02:00
Clifford Wolf b6db2d9b33 Moved dfflibmap from passes/dfflibmap to passes/techmap 2013-10-16 15:32:26 +02:00
Clifford Wolf 845590aa8e Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";' 
Patch by Tim Edwards
 2013-10-16 06:32:35 +02:00
Clifford Wolf 288ba9618a Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00
Clifford Wolf f8107ab7fc Some minor documentation fixes 2013-08-21 12:16:44 +02:00
Clifford Wolf 1af1cebb64 Minor fixes in abc build instructions and abc pass 2013-08-20 09:46:05 +02:00
Clifford Wolf 2f3da54f26 Added sat -ignore_div_by_zero switch 2013-08-15 11:40:01 +02:00
Clifford Wolf d0e93e04d1 Added eval -brute_force_equiv_checker_x mode 2013-08-15 11:09:30 +02:00
Clifford Wolf a5836af172 Added "clean -purge" and ";;;" support 2013-08-11 13:59:14 +02:00
Clifford Wolf 080f0aac34 Added ";;" as shortcut for "; clean;" 2013-08-11 13:33:38 +02:00
Clifford Wolf 6068b8902f freduce performance fix 2013-08-10 15:03:13 +02:00
Clifford Wolf 376150c926 Added techmap -opt mode 2013-08-09 15:20:22 +02:00
Clifford Wolf 05483619f0 Some fixes to improve determinism 2013-08-09 12:42:32 +02:00
Clifford Wolf d97782b848 Sort ctrl signals in fsm_extract 2013-08-08 15:46:00 +02:00
Clifford Wolf 6a40e46a04 Added -try option to freduce pass 2013-08-08 10:56:27 +02:00
Clifford Wolf 8cd153612e Added "clean" command (less verbose opt_clean) 2013-08-08 10:53:37 +02:00
Clifford Wolf 56e01ce389 Fixed topological ordering in freduce pass 2013-08-07 19:38:19 +02:00
Clifford Wolf e729857647 Improved handling of private names in opt_clean and rename commands 2013-08-07 18:39:49 +02:00
Clifford Wolf 653750faac Small bugfixes in freduce pass 2013-08-06 15:53:09 +02:00
Clifford Wolf 6efca9ea5a Added freduce command 2013-08-06 15:04:52 +02:00
Clifford Wolf 0f38008ed3 Added "design" command (-reset, -save, -load) 2013-07-27 14:27:51 +02:00
Clifford Wolf 88d0829d65 Automatically run "proc" on extract map files 2013-07-24 20:19:08 +02:00
Clifford Wolf ad9bbcbf40 Added $lut cells and abc lut mapping support 2013-07-23 16:19:34 +02:00
Clifford Wolf a9fefc6ce1 Bugfixes for empty signal vectors 2013-07-10 12:52:29 +02:00
Clifford Wolf cf885c4a28 Added opt_clean -purge option 2013-07-07 12:59:30 +02:00
Clifford Wolf 0c0197cf45 Fixed handling of $eq and $ne in opt_const 2013-07-07 12:59:00 +02:00
Clifford Wolf 101491132f Added SAT support for -all/-max with -verify 2013-06-23 13:28:30 +02:00
Clifford Wolf 46b177eb8a Merge branch 'master' of github.com:cliffordwolf/yosys 2013-06-20 12:49:28 +02:00
Clifford Wolf 8fbb5b6240 Added timout functionality to SAT solver 2013-06-20 12:49:10 +02:00
Clifford Wolf a6aeb3dbf0 Added renaming of wires and cells to "rename" command 2013-06-19 16:55:43 +02:00
Clifford Wolf 21e38bed98 Added "eval" pass 2013-06-19 09:30:37 +02:00
Clifford Wolf 48aa72ae8f Added splitnets command 2013-06-18 17:11:36 +02:00
Clifford Wolf c09b66b2a1 Added support for "assign" statements in abc vlparse 2013-06-15 13:50:38 +02:00
Clifford Wolf 6d7b5f9064 Fixed even more ConstEval bugs found using xsthammer 2013-06-14 17:50:26 +02:00