yosys

Commit Graph

Author	SHA1	Message	Date
Claire Xenia Wolf	92e705cb51	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
Dan Ravensloft	2e37e62e6b	synth_intel_alm: alternative synthesis for Intel FPGAs By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).	2020-04-15 11:40:41 +02:00

Author

SHA1

Message

Date

Claire Xenia Wolf

92e705cb51

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

Dan Ravensloft

2e37e62e6b

synth_intel_alm: alternative synthesis for Intel FPGAs

By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).

2020-04-15 11:40:41 +02:00

2 Commits