Eddie Hung
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19ec54f956
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write_aiger: make more robust
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2020-01-06 10:18:59 -08:00 |
Eddie Hung
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b5f60e055d
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write_xaiger to pad, not abc9_ops -prep_holes
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2020-01-05 10:20:24 -08:00 |
Eddie Hung
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6556a1347a
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Fix when -dff not given
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2020-01-04 09:17:01 -08:00 |
Eddie Hung
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930f03e883
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Call -prep_holes before aigmap; fix topo ordering
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2020-01-03 15:38:18 -08:00 |
Eddie Hung
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a819656972
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WIP
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2020-01-03 14:59:55 -08:00 |
Eddie Hung
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559f3379e8
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Preserve topo ordering from -prep_holes to write_xaiger
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2020-01-03 14:37:58 -08:00 |
Eddie Hung
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bb70915fb8
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WIP
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2020-01-03 13:21:56 -08:00 |
Eddie Hung
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e1f494ab1d
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WIP
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2020-01-03 13:08:52 -08:00 |
Eddie Hung
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e62eb02c1d
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Restore write_xaiger's holes_mode since port_id order causes QoR
regressions inside abc9
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2020-01-03 12:32:05 -08:00 |
Eddie Hung
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dedea5a58d
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Cleanup
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2020-01-02 17:25:14 -08:00 |
Eddie Hung
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c28bea0382
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Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
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2020-01-02 15:57:35 -08:00 |
Eddie Hung
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07feedfa73
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write_xaiger: get rid of external_bits dict
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2020-01-02 15:32:58 -08:00 |
Eddie Hung
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8e507bd807
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abc9 -keepff -> -dff; refactor dff operations
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2020-01-02 12:36:54 -08:00 |
Eddie Hung
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11577b46fc
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Get rid of (* abc9_keep *) in write_xaiger too
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2020-01-01 08:38:23 -08:00 |
Eddie Hung
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ac808c5e2a
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attributes.count() -> get_bool_attribute()
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2020-01-01 08:33:32 -08:00 |
Eddie Hung
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96db05aaef
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parse_xaiger to not take box_lookup
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2019-12-31 17:06:03 -08:00 |
Eddie Hung
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cac7f5d82e
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Do not re-order carry chain ports, just precompute iteration order
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2019-12-31 16:12:40 -08:00 |
Eddie Hung
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134e70e8e7
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write_xaiger: be more precise with ff_bits, remove ff_aig_map
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2019-12-31 10:21:11 -08:00 |
Eddie Hung
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3798fa3bea
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Retry getting rid of write_xaiger's holes_mode
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2019-12-31 09:59:17 -08:00 |
Eddie Hung
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436c96e2fb
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Revert "Get rid of holes_mode"
This reverts commit 7997e2a90f .
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2019-12-30 23:29:14 -08:00 |
Eddie Hung
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7997e2a90f
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Get rid of holes_mode
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2019-12-30 20:15:09 -08:00 |
Eddie Hung
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b42b64e8ed
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Move Pass::call() out of abc9_ops into abc9
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2019-12-30 19:23:54 -08:00 |
Eddie Hung
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88334cab89
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Cleanup
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2019-12-30 18:49:33 -08:00 |
Eddie Hung
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65baefecd3
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Rid unnecessary if
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2019-12-30 18:26:35 -08:00 |
Eddie Hung
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e2bbe33a88
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Get rid of holes_mode
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2019-12-30 18:24:29 -08:00 |
Eddie Hung
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b50de28c04
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Add abc9_ops -prep_holes
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2019-12-30 18:00:49 -08:00 |
Eddie Hung
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0735572934
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write_xaiger to use scratchpad for stats; cleanup abc9
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2019-12-30 15:35:33 -08:00 |
Eddie Hung
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d1fccd5a2d
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Remove unused
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2019-12-30 14:35:52 -08:00 |
Eddie Hung
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3cbbae251f
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Call "proc" if processes inside whiteboxes
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2019-12-30 14:33:05 -08:00 |
Eddie Hung
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405e974fe5
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-30 14:31:42 -08:00 |
Eddie Hung
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d7ada66497
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Add "synth_xilinx -dff" option, cleanup abc9
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2019-12-30 14:13:16 -08:00 |
Eddie Hung
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237415e78c
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write_xaiger: inherit port ordering from original module
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2019-12-27 16:44:18 -08:00 |
Eddie Hung
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a56d6970f2
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Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"
This reverts commit 92654f73ea , reversing
changes made to 3e14ff1667 .
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2019-12-27 16:05:58 -08:00 |
Eddie Hung
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9e6632c40a
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Merge branch 'master' of github.com:YosysHQ/yosys
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2019-12-27 15:37:26 -08:00 |
Eddie Hung
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3d4644804e
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write_xaiger: simplify c{i,o}_bits
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2019-12-27 15:37:17 -08:00 |
David Shah
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df31ade3b3
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Revert "write_xaiger: only instantiate each whitebox cell type once"
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2019-12-27 23:25:20 +00:00 |
Eddie Hung
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dd503a5f3f
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Really fix it!
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2019-12-27 15:18:55 -08:00 |
Eddie Hung
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49881b4468
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write_xaiger: fix arrival times for non boxes
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2019-12-27 11:30:18 -08:00 |
Eddie Hung
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6eadd4390a
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write_xaiger to opt instead of just clean whiteboxes
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2019-12-23 08:35:53 -08:00 |
Eddie Hung
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a75e08c709
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write_xaiger: only instantiate each whitebox cell type once
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2019-12-20 13:07:24 -08:00 |
Eddie Hung
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10e82e103f
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Revert "Optimise write_xaiger"
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2019-12-20 12:05:45 -08:00 |
Eddie Hung
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5f50e4f112
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Cleanup xaiger, remove unnecessary complexity with inout
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2019-12-17 15:45:26 -08:00 |
Eddie Hung
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e82a9bc642
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Do not sigmap
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2019-12-17 00:03:03 -08:00 |
Eddie Hung
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2e71130700
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Revert "Use sigmap signal"
This reverts commit 42f990f3a6 .
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2019-12-17 00:00:07 -08:00 |
Eddie Hung
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42f990f3a6
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Use sigmap signal
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2019-12-16 16:49:42 -08:00 |
Eddie Hung
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b19fc8839b
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Skip $inout transformation if not a PI
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2019-12-16 14:39:13 -08:00 |
Eddie Hung
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78c0246d4a
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Revert "write_xaiger: use sigmap bits more consistently"
This reverts commit 6c340112fe .
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2019-12-16 14:35:35 -08:00 |
Eddie Hung
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6c340112fe
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write_xaiger: use sigmap bits more consistently
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2019-12-16 10:21:57 -08:00 |
Eddie Hung
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91467938c4
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Stray newline
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2019-12-06 17:08:19 -08:00 |
Eddie Hung
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f2ac36de4a
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write_xaiger to inst each cell type once, do not call techmap/aigmap
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2019-12-06 17:06:10 -08:00 |
Eddie Hung
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1f96de04c9
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Fix writing non-whole modules, including inouts and keeps
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2019-12-06 16:19:10 -08:00 |
Eddie Hung
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a682a3cf93
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write_xaiger to support part-selected modules again
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2019-12-05 17:54:43 -08:00 |
Eddie Hung
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c6ee2fb482
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Cleanup
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2019-12-03 19:21:47 -08:00 |
Eddie Hung
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df52bc80d8
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write_xaiger to consume abc9_init attribute for abc9_flops
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2019-12-03 18:47:44 -08:00 |
Eddie Hung
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419ca5c207
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Revert "Fold loop"
This reverts commit a30d5e1cc3 .
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2019-11-27 21:55:56 -08:00 |
Eddie Hung
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449b1d2c6f
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Add comment, use sigmap
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2019-11-27 13:20:12 -08:00 |
Eddie Hung
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403214f44d
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Revert "Fold loop"
This reverts commit da51492dbc .
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2019-11-27 12:35:25 -08:00 |
Eddie Hung
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5e67df38ed
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latch -> box
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2019-11-26 22:59:05 -08:00 |
Eddie Hung
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a30d5e1cc3
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Fold loop
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2019-11-26 21:57:50 -08:00 |
Eddie Hung
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68717dd03b
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Do not sigmap keep bits inside write_xaiger
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2019-11-26 21:57:50 -08:00 |
Eddie Hung
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7136cee6b4
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xaiger: do not promote output wires
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2019-11-26 21:55:37 -08:00 |
Eddie Hung
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99702efaba
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xaiger: do not promote output wires
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2019-11-26 19:03:02 -08:00 |
Eddie Hung
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da51492dbc
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Fold loop
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2019-11-25 15:43:37 -08:00 |
Eddie Hung
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7f0914a408
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Do not sigmap keep bits inside write_xaiger
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2019-11-25 15:42:07 -08:00 |
Eddie Hung
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81548d1ef9
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write_xaiger back to working with whole modules only
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2019-11-22 16:52:17 -08:00 |
Eddie Hung
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8ef241c6f4
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Revert "write_xaiger to not use module POs but only write outputs if driven"
This reverts commit 0ab1e496dc .
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2019-11-22 13:24:28 -08:00 |
Eddie Hung
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0ab1e496dc
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write_xaiger to not use module POs but only write outputs if driven
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2019-11-21 16:19:28 -08:00 |
Eddie Hung
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929beda19c
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abc9 to support async flops $_DFF_[NP][NP][01]_
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2019-11-19 16:57:26 -08:00 |
Eddie Hung
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09ee96e8c2
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-19 15:40:39 -08:00 |
Clifford Wolf
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5110a34dd7
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Fix write_aiger bug added in 524af21
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-11-04 14:25:13 +01:00 |
Eddie Hung
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b2e34f932a
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Rename $currQ to $abc9_currQ
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2019-10-07 15:31:43 -07:00 |
Eddie Hung
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90a954bb9c
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Get rid of latch_* in write_xaiger
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2019-10-07 13:09:13 -07:00 |
Eddie Hung
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1504ca2cd9
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Remove "write_xaiger -zinit"
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2019-10-07 11:58:49 -07:00 |
Eddie Hung
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e1554b56dd
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Add comment on default flop init
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2019-10-07 11:56:17 -07:00 |
Eddie Hung
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d9fba95177
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Get rid of output_port lookup
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2019-10-07 11:49:06 -07:00 |
Eddie Hung
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3879ca1398
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Do not require changes to cells_sim.v; try and work out comb model
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2019-10-05 22:55:18 -07:00 |
Eddie Hung
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3c6e5d82a6
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Error if $currQ not found
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2019-10-05 09:06:13 -07:00 |
Eddie Hung
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7959e9d6b2
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Fix merge issues
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2019-10-04 17:21:14 -07:00 |
Eddie Hung
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7a45cd5856
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Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
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2019-10-04 16:58:55 -07:00 |
Eddie Hung
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aae2b9fd9c
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Rename abc_* names/attributes to more precisely be abc9_*
|
2019-10-04 11:04:10 -07:00 |
Eddie Hung
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1b96d29174
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No need to punch ports at all
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2019-09-30 17:02:20 -07:00 |
Eddie Hung
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e529872b01
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Remove need for $currQ port connection
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2019-09-30 16:33:40 -07:00 |
Eddie Hung
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eecfdda614
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Cleanup
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2019-09-30 15:24:03 -07:00 |
Eddie Hung
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74678227c7
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Use a cell_cache to instantiate once rather than opt_merge call
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2019-09-30 13:21:07 -07:00 |
Eddie Hung
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a6994c5f16
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scc call on active module module only, plus cleanup
|
2019-09-30 12:57:19 -07:00 |
Eddie Hung
|
bd8356799a
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Use derived module
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2019-09-30 12:34:28 -07:00 |
Eddie Hung
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1123c09588
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-29 19:39:12 -07:00 |
Eddie Hung
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8474c5b366
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Merge pull request #1359 from YosysHQ/xc7dsp
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
|
2019-09-29 11:26:22 -07:00 |
Eddie Hung
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f3e150d9a5
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-29 09:21:51 -07:00 |
Eddie Hung
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79b6edb639
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Big rework; flop info now mostly in cells_sim.v
|
2019-09-28 23:48:17 -07:00 |
Miodrag Milanovic
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0c380f0855
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Add aiger and protobuf backends binary support
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2019-09-28 09:51:48 +02:00 |
Miodrag Milanovic
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d0493925ec
|
Support binary files for backends, fixes #1407
|
2019-09-28 09:36:18 +02:00 |
Eddie Hung
|
cfa6dd61ef
|
Use abc_mergeability attr for "r" extension
|
2019-09-27 18:41:43 -07:00 |
Eddie Hung
|
dc154c39a8
|
Fix infinite recursion
|
2019-09-27 17:45:49 -07:00 |
Eddie Hung
|
8f5710c464
|
Merge remote-tracking branch 'origin/master' into xaig_dff
|
2019-09-27 15:14:31 -07:00 |
Eddie Hung
|
44374b1b2b
|
"abc_padding" attr for blackbox outputs that were padded, remove them later
|
2019-09-23 21:58:40 -07:00 |
Eddie Hung
|
c340fbfab2
|
Force $inout.out ports to begin with '$' to indicate internal
|
2019-09-23 21:58:04 -07:00 |
Eddie Hung
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2d9484c12c
|
When two boxes connect to each other, need not be a (* keep *)
|
2019-09-19 15:40:28 -07:00 |
Clifford Wolf
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779ce3537f
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Add "write_aiger -L"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-09-18 13:33:02 +02:00 |
Eddie Hung
|
e9bb252e77
|
Recognise built-in types (e.g. $_DFF_*)
|
2019-08-30 20:15:09 -07:00 |