Clifford Wolf
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8a4c6e6563
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Merge tag 'yosys-0.9'
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2019-08-26 11:14:22 +02:00 |
Clifford Wolf
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1979e0b1f2
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Yosys 0.9
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-26 10:37:53 +02:00 |
Clifford Wolf
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a3de83ef4a
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Merge pull request #1112 from acw1251/pyosys_sigsig_issue
Fixed pyosys commands returning RTLIL::SigSig
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2019-08-25 11:22:02 +02:00 |
Eddie Hung
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dc87372a97
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Wire with init on FF part, 1'bx on non-FF part
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2019-08-24 15:05:44 -07:00 |
Clifford Wolf
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dc9c47b5af
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Merge pull request #1327 from YosysHQ/clifford/pmgen
Add pmgen slices and choices
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2019-08-24 08:38:49 +02:00 |
Eddie Hung
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7911143827
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Create new $__XILINX_SHREG_ cell for variable length too
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2019-08-23 18:15:49 -07:00 |
Eddie Hung
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a048fc93e8
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Do not allow Q of last cell of variable length SRL to be (* keep *)
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2019-08-23 18:15:24 -07:00 |
Eddie Hung
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ee9f6e6243
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Also add first.Q to chain_bits since variable length
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2019-08-23 18:14:06 -07:00 |
Eddie Hung
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70ce3d0670
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Do not enforce !EN_POLARITY on $dffe
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2019-08-23 18:11:28 -07:00 |
Eddie Hung
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188b49378a
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Create new cell for fixed length SRL
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2019-08-23 17:25:30 -07:00 |
Eddie Hung
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e081303ee8
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Cleanup FDRE matching
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2019-08-23 17:23:52 -07:00 |
Eddie Hung
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d7051b90de
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Add undocumented feature
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2019-08-23 16:41:32 -07:00 |
Eddie Hung
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54488cfb82
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Oops don't need a finally block
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2019-08-23 16:39:37 -07:00 |
Eddie Hung
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83e2d87fb8
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Keep track of bits in variable length chain, to check for taps
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2019-08-23 16:21:10 -07:00 |
Eddie Hung
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f2d4814284
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Don't forget $dff has no EN
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2019-08-23 16:14:57 -07:00 |
Eddie Hung
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2217d926a9
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Same for variable length
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2019-08-23 16:13:16 -07:00 |
Eddie Hung
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b1caf7be5e
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Filter on en_port for fixed length
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2019-08-23 16:09:46 -07:00 |
Eddie Hung
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513af10d77
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Check clock is consistent
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2019-08-23 15:18:26 -07:00 |
Eddie Hung
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c762618783
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Fix last_cell.D
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2019-08-23 15:08:49 -07:00 |
Eddie Hung
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ca5de78e76
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Revert "Add a unique argument to pmgen's nusers()"
This reverts commit 1d88887cfd .
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2019-08-23 15:04:00 -07:00 |
Eddie Hung
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e85e6e8d45
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Revert "Fix polarity"
This reverts commit 9cd23cf0fe .
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2019-08-23 15:03:42 -07:00 |
Eddie Hung
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9cd23cf0fe
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Fix polarity
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2019-08-23 14:49:34 -07:00 |
Eddie Hung
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c2757613b6
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Check for non unique nusers/fanouts
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2019-08-23 14:32:36 -07:00 |
Eddie Hung
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1d88887cfd
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Add a unique argument to pmgen's nusers()
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2019-08-23 14:32:17 -07:00 |
Eddie Hung
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8ecfd55d5a
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Update doc
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2019-08-23 14:16:41 -07:00 |
Eddie Hung
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3d7f4aa0c8
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Remove (* init *) entry when consumed into SRL
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2019-08-23 13:56:01 -07:00 |
Eddie Hung
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3fa826254f
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Merge branch 'xaig_arrival' of github.com:YosysHQ/yosys into xaig_arrival
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2019-08-23 13:46:17 -07:00 |
Eddie Hung
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48c424e45b
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Cleanup
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2019-08-23 13:46:05 -07:00 |
Eddie Hung
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3c1c376fb1
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Revert to upstream
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2019-08-23 13:22:37 -07:00 |
Eddie Hung
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455da57272
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Fix spacing
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2019-08-23 13:21:21 -07:00 |
Eddie Hung
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85d39653ac
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Remove unused model
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2019-08-23 13:20:29 -07:00 |
Eddie Hung
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967a36c125
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indo -> into
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2019-08-23 13:16:50 -07:00 |
Eddie Hung
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a1f78eab04
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indo -> into
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2019-08-23 13:15:41 -07:00 |
Eddie Hung
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5939ffdc07
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Forgot to slice
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2019-08-23 13:06:59 -07:00 |
Eddie Hung
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242b3083ea
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Cope with possibility that D could connect to Q on same cell
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2019-08-23 13:06:31 -07:00 |
Eddie Hung
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4a4e28b55e
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Revert earliest to gcc-4.8, compile iverilog with default compiler
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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b3dc28cf65
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Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!"
This reverts commit c82b2fa31f .
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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fcb102d60e
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Remove .0 from clang-8.0
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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fdc438e551
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Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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bf40f2f895
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bionic -> xenial as its on whitelist
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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43927e5910
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Bump gcc from 4.8 to 4.9 as undefined reference
... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
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2019-08-23 12:29:50 -07:00 |
Eddie Hung
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cee30deef5
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Mention shregmap -tech xilinx is superseded
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2019-08-23 12:24:25 -07:00 |
Eddie Hung
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08139aa53a
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xilinx_srl now copes with word-level flops $dff{,e}
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2019-08-23 12:22:46 -07:00 |
Eddie Hung
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18b64609c2
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xilinx_srl to use 'slice' features of pmgen for word level
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2019-08-23 12:22:06 -07:00 |
Eddie Hung
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f4fd41d5d2
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Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
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2019-08-23 11:35:06 -07:00 |
Eddie Hung
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78b7d8f531
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
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2019-08-23 11:32:44 -07:00 |
Eddie Hung
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e658d472c8
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Put attributes above port
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2019-08-23 11:31:20 -07:00 |
Eddie Hung
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d672b1ddec
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-23 11:26:55 -07:00 |
Eddie Hung
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20f4d191b5
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Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-23 11:24:19 -07:00 |
Eddie Hung
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509c353fe9
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Forgot one
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2019-08-23 11:23:50 -07:00 |