Eddie Hung
60026842b2
Tweak
2019-04-22 17:59:56 -07:00
Eddie Hung
26e461f47d
Fix for A_WIDTH == 2 but B_WIDTH==3
2019-04-22 17:58:28 -07:00
Eddie Hung
1fa2c36fbd
Trim A_WIDTH by Y_WIDTH-1
2019-04-22 17:14:11 -07:00
Eddie Hung
69863f7698
Add comment
2019-04-22 16:58:44 -07:00
Eddie Hung
61161faefc
Fix for mux_case_* mappings
2019-04-22 16:56:18 -07:00
Eddie Hung
ac1e13819e
Fix for non-pow2 width muxes
2019-04-22 14:26:13 -07:00
Eddie Hung
75b96b1aff
Add synth_xilinx -nomux option
2019-04-22 12:36:15 -07:00
Eddie Hung
79fb291dbe
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 12:14:37 -07:00
Eddie Hung
4cfef7897f
Merge branch 'xaig' into xc7mux
2019-04-22 11:58:59 -07:00
Eddie Hung
4486a98fd5
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-22 11:45:49 -07:00
Eddie Hung
ec88129a5c
Update help message
2019-04-22 11:38:23 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Eddie Hung
0e76718720
Move 'shregmap -tech xilinx' into map_cells
2019-04-22 10:45:39 -07:00
Eddie Hung
e300b1922c
Merge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 10:36:27 -07:00
Clifford Wolf
0e7901e45c
Merge pull request #941 from Wren6991/sim_lib_io_clke
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ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
2019-04-22 09:11:13 +02:00
Clifford Wolf
913659d644
Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
2019-04-22 09:09:27 +02:00
Clifford Wolf
cf1ba46fa0
Re-added clean after techmap in synth_xilinx
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 09:03:11 +02:00
Clifford Wolf
cbd9b8a3f3
Merge pull request #916 from YosysHQ/map_cells_before_map_luts
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synth_xilinx to map_cells before map_luts
2019-04-22 09:01:00 +02:00
Clifford Wolf
19fd411e77
Merge pull request #911 from mmicko/gowin-nobram
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Make nobram false by default for gowin
2019-04-22 08:58:09 +02:00
Eddie Hung
d342b5b135
Tidy up, fix for -nosrl
2019-04-21 15:33:03 -07:00
Eddie Hung
d7f0700bae
Convert to use #945
2019-04-21 15:19:02 -07:00
Eddie Hung
726e2da8f2
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-21 14:28:55 -07:00
Eddie Hung
a3371e118b
Merge branch 'master' into map_cells_before_map_luts
2019-04-21 14:24:50 -07:00
Eddie Hung
ae95aba60a
Add comments
2019-04-21 14:16:59 -07:00
Eddie Hung
d99422411f
Use new pmux2shiftx from #944 , remove my old attempt
2019-04-21 14:16:34 -07:00
Luke Wren
71da836300
ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments
2019-04-21 21:40:11 +01:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Eddie Hung
13ad19482f
Merge remote-tracking branch 'origin' into xc7srl
2019-04-20 10:41:43 -07:00
Eddie Hung
af4652522f
ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set
2019-04-19 21:09:55 -07:00
Eddie Hung
2776925bcf
Make SB_DFF whitebox
2019-04-19 08:36:38 -07:00
Eddie Hung
19b660ff6e
Fix SB_DFF comb model
2019-04-18 23:07:16 -07:00
Eddie Hung
0919f36b88
Missing close bracket
2019-04-18 17:50:11 -07:00
Eddie Hung
cf66416110
Annotate SB_DFF* with abc_flop and abc_box_id
2019-04-18 17:46:53 -07:00
Eddie Hung
ca1eb98a97
Add SB_DFF* to boxes
2019-04-18 17:46:32 -07:00
Eddie Hung
4c327cf316
Use new -wb flag for ABC flow
2019-04-18 10:32:41 -07:00
Eddie Hung
9278192efe
Also update Makefile.inc
2019-04-18 09:58:34 -07:00
Eddie Hung
7b6ab937c1
Make SB_LUT4 a blackbox
2019-04-18 09:05:22 -07:00
Eddie Hung
8024f41897
Fix rename
2019-04-18 09:04:34 -07:00
Eddie Hung
ed5e75ed7d
Rename to abc_*.{box,lut}
2019-04-18 09:02:58 -07:00
Eddie Hung
6008bb7002
Revert "synth_* with -retime option now calls abc with -D 1 as well"
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This reverts commit 9a6da9a79a
.
2019-04-18 07:59:16 -07:00
Eddie Hung
0642baabbc
Merge branch 'master' into eddie/fix_retime
2019-04-18 07:57:17 -07:00
Eddie Hung
8fd455c910
Update Makefile.inc too
2019-04-17 15:19:48 -07:00
Eddie Hung
c795e14d25
Reduce to three devices: hx, lp, u
2019-04-17 15:19:02 -07:00
Eddie Hung
5c0853fc51
Add up5k timings
2019-04-17 15:10:39 -07:00
Eddie Hung
4b520ae627
Fix grammar
2019-04-17 15:10:22 -07:00
Eddie Hung
3105a8a653
Update error message
2019-04-17 15:07:44 -07:00
Eddie Hung
6f3e5297db
Add "-device" argument to synth_ice40
2019-04-17 15:04:46 -07:00
Eddie Hung
671cca59a9
Missing abc_flop_q attribute on SPRAM
2019-04-17 14:44:08 -07:00
Eddie Hung
437fec0d88
Map to SB_LUT4 from fastest input first
2019-04-17 13:01:17 -07:00
Eddie Hung
58847df1b9
Mark seq output ports with "abc_flop_q" attr
2019-04-17 12:27:45 -07:00
Eddie Hung
1eade06671
Also update Makefile.inc
2019-04-17 12:27:02 -07:00
Eddie Hung
4fb9ccfcd8
synth_ice40 to use renamed files
2019-04-17 12:22:03 -07:00
Eddie Hung
42c33db22c
Rename to abc.*
2019-04-17 12:15:34 -07:00
Eddie Hung
c1ebe51a75
Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"
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This reverts commit a7632ab332
.
2019-04-17 11:10:20 -07:00
Eddie Hung
a7632ab332
Try using an ICE40_CARRY_LUT primitive to avoid ABC issues
2019-04-17 11:10:04 -07:00
Eddie Hung
17fb6c3522
Fix spacing
2019-04-17 08:40:50 -07:00
Eddie Hung
743c164eee
Add SB_LUT4 to box library
2019-04-16 17:34:11 -07:00
Eddie Hung
7980118d74
Add ice40 box files
2019-04-16 16:39:30 -07:00
Eddie Hung
cbb85e40e8
Add MUXCY and XORCY to cells_box.v
2019-04-16 14:53:28 -07:00
Eddie Hung
aece97024d
Fix spacing
2019-04-16 13:16:20 -07:00
Eddie Hung
53b19ab1f5
Make cells.box whiteboxes not blackboxes
2019-04-16 12:43:14 -07:00
Eddie Hung
5189695362
read_verilog cells_box.v before techmap
2019-04-16 12:41:56 -07:00
Eddie Hung
d259e6dc14
synth_xilinx: before abc read +/xilinx/cells_box.v
2019-04-16 11:21:46 -07:00
Eddie Hung
3ac4977b70
Add +/xilinx/cells_box.v containing models for ABC boxes
2019-04-16 11:21:03 -07:00
Eddie Hung
8c6cf07acf
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
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This reverts commit 8fbbd9b129
.
2019-04-16 11:14:59 -07:00
Eddie Hung
8fbbd9b129
Add abc_box_id attribute to MUXF7/F8 cells
2019-04-15 22:25:09 -07:00
Eddie Hung
538592067e
Merge branch 'xaig' into xc7mux
2019-04-15 22:04:20 -07:00
Diego
f9272fc56d
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
2019-04-12 23:40:02 -05:00
Eddie Hung
04e466d5e4
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-12 12:28:37 -07:00
Eddie Hung
f77da46a87
Merge remote-tracking branch 'origin/master' into xaig
2019-04-12 12:21:48 -07:00
Eddie Hung
db1a5ec6a2
Merge pull request #928 from litghost/add_xc7_sim_models
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Add additional cells sim models for core 7-series primitives.
2019-04-12 11:52:45 -07:00
Eddie Hung
8228b593ef
Merge remote-tracking branch 'origin/master' into xc7mux
2019-04-12 09:46:07 -07:00
Keith Rothman
1f9235ede5
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-12 09:35:15 -07:00
Diego
643ae9bfc5
Fixing issues in CycloneV cell sim
2019-04-11 19:59:03 -05:00
Eddie Hung
233edf00fe
Fix cells_map.v some more
2019-04-11 10:48:14 -07:00
Eddie Hung
8658b56a08
More fine tuning
2019-04-11 10:08:05 -07:00
Eddie Hung
0ec8564099
Fix cells_map.v
2019-04-11 10:04:58 -07:00
Eddie Hung
bca3779657
Fix typo
2019-04-11 09:25:19 -07:00
Eddie Hung
87b8d29a90
Juggle opt calls in synth_xilinx
2019-04-11 09:13:39 -07:00
Eddie Hung
cd7b2de27f
WIP for cells_map.v -- maybe working?
2019-04-10 18:05:09 -07:00
Eddie Hung
3d577586fd
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
2019-04-10 16:15:23 -07:00
Eddie Hung
3f5dab0d09
Fix for when B_SIGNED = 1
2019-04-10 14:51:10 -07:00
Eddie Hung
32561332b2
Update doc for synth_xilinx
2019-04-10 14:48:58 -07:00
Eddie Hung
17a02df05c
ff_map.v after abc
2019-04-10 12:36:06 -07:00
Eddie Hung
1ec949d5ed
Tidy up
2019-04-10 09:02:42 -07:00
Eddie Hung
526aef9c2a
Move map_cells to before map_luts
2019-04-10 08:50:31 -07:00
Eddie Hung
e0b46eb4cb
WIP for $shiftx to wide mux
2019-04-10 08:49:55 -07:00
Eddie Hung
4dac9818bd
Update LUT delays
2019-04-10 08:49:39 -07:00
Eddie Hung
9a6da9a79a
synth_* with -retime option now calls abc with -D 1 as well
2019-04-10 08:32:53 -07:00
Eddie Hung
3e368593eb
Add cells.lut to techlibs/xilinx/
2019-04-09 14:33:37 -07:00
Eddie Hung
fd88ab5c83
synth_xilinx to call abc with -lut +/xilinx/cells.lut
2019-04-09 14:32:39 -07:00
Eddie Hung
b9e19071b8
Add delays to cells.box
2019-04-09 14:32:10 -07:00
Keith Rothman
e107ccdde8
Fix LUT6_2 definition.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 11:43:19 -07:00
Eddie Hung
f2042fc7c4
synth_xilinx with abc9 to use -box
2019-04-09 11:01:46 -07:00
Eddie Hung
2ae26b986c
Add techlibs/xilinx/cells.box
2019-04-09 10:58:58 -07:00
Eddie Hung
3fc474aa73
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
2019-04-09 10:06:44 -07:00
Keith Rothman
5e0339855f
Add additional cells sim models for core 7-series primatives.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-04-09 09:01:53 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Eddie Hung
1d526b7f06
Call shregmap twice -- once for variable, another for fixed
2019-04-05 17:35:49 -07:00
Eddie Hung
a5f33b5409
Move dffinit til after abc
2019-04-05 16:20:43 -07:00
Eddie Hung
0364a5d811
Merge branch 'eddie/fix_retime' into xc7srl
2019-04-05 15:46:18 -07:00
Eddie Hung
9758701574
Move techamp t:$_DFF_?N? to before abc call
2019-04-05 15:39:05 -07:00
Eddie Hung
23a6533e98
Retry
2019-04-05 15:31:54 -07:00
Eddie Hung
8b6085254a
Resolve @daveshah1 comment, update synth_xilinx help
2019-04-05 15:15:13 -07:00
Eddie Hung
ff0912c75e
synth_xilinx to techmap FFs after abc call, otherwise -retime fails
2019-04-05 14:43:06 -07:00
Eddie Hung
544843da71
techmap inside map_cells stage
2019-04-05 12:55:52 -07:00
Eddie Hung
7b7ddbdba7
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 08:13:34 -07:00
Eddie Hung
e3f20b17af
Missing techmap entry in help
2019-04-04 08:13:10 -07:00
Eddie Hung
2fb02247a7
Use soft-logic, not LUT3 instantiation
2019-04-04 08:10:40 -07:00
Eddie Hung
572603409c
Merge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 07:54:42 -07:00
Eddie Hung
d9cb787391
synth_xilinx to map_cells before map_luts
2019-04-04 07:48:13 -07:00
Eddie Hung
77755b5a66
Cleanup comments
2019-04-04 07:41:40 -07:00
Eddie Hung
736e19f02d
t:$dff* -> t:$dff t:$dffe
2019-04-04 07:39:19 -07:00
Eddie Hung
0e2d929cea
-nosrl meant when -nobram
2019-04-03 08:28:07 -07:00
Eddie Hung
ff385a5ad0
Remove duplicate STARTUPE2
2019-04-03 08:14:09 -07:00
Eddie Hung
88630cd02c
Disable shregmap in synth_xilinx if -retime
2019-04-03 07:14:20 -07:00
Miodrag Milanovic
df92e9bdc2
Make nobram false by default for gowin
2019-04-02 19:21:01 +02:00
Eddie Hung
f9fb05cf66
synth_xilinx to use shregmap with -minlen 3
2019-03-25 13:18:55 -07:00
Eddie Hung
46753cf89f
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 13:10:42 -07:00
David Shah
46f6a60d58
xilinx: Add keep attribute where appropriate
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-22 13:57:17 +00:00
Eddie Hung
4cc6b3e942
Add '-nosrl' option to synth_xilinx
2019-03-21 15:04:44 -07:00
Eddie Hung
81c207fb9b
Fine tune cells_map.v
2019-03-20 10:55:14 -07:00
Eddie Hung
505e4c2d59
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
2019-03-19 21:58:05 -07:00
Eddie Hung
5445cd4d00
Add support for variable length Xilinx SRL > 128
2019-03-19 17:44:33 -07:00
Eddie Hung
ae2a625d05
Restore original synth_xilinx commands
2019-03-19 16:14:08 -07:00
Eddie Hung
9156e18f92
Fix spacing
2019-03-19 16:12:32 -07:00
Eddie Hung
f239cb821e
Fix INIT for variable length SRs that have been bumped up one
2019-03-19 14:54:43 -07:00
Eddie Hung
24553326dd
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 13:11:30 -07:00
Clifford Wolf
fe1fb1336b
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-19 20:30:28 +01:00
Eddie Hung
fadeadb8c8
Only accept <128 for variable length, only if $shiftx exclusive
2019-03-16 08:51:13 -07:00
Eddie Hung
29a8d4745e
Cleanup synth_xilinx
2019-03-15 23:01:40 -07:00
Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Eddie Hung
e7ef7fa443
Reverse bits in INIT parameter for Xilinx, since MSB is shifted first
2019-03-14 09:38:42 -07:00
Eddie Hung
af5706c2a3
Misspell
2019-03-14 09:06:56 -07:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
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This reverts commit 26ecbc1aee
.
2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Eddie Hung
79b4a275ce
Fix cells_map for SRL
2019-03-14 08:09:48 -07:00
Eddie Hung
edca2f1163
Move shregmap until after first techmap
2019-03-13 17:13:52 -07:00
Eddie Hung
24f129ddfb
Refactor $__SHREG__ in cells_map.v
2019-03-13 16:17:54 -07:00
Clifford Wolf
9284cf92b8
Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:14:18 +01:00
Clifford Wolf
ff4c2a14ae
Fix typo in ice40_braminit help msg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-09 13:24:55 -08:00
Clifford Wolf
2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit
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iCE40 BRAM primitives init from file
2019-03-09 13:24:10 -08:00
Sylvain Munaut
5b6f591033
ice40: Run ice40_braminit pass by default
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
Sylvain Munaut
e71055cfe8
ice40: Add ice40_braminit pass to allow initialization of BRAM from file
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This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
Clifford Wolf
350dfd3745
Add link to SF2 / igloo2 macro library guide
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 09:08:26 -08:00
Clifford Wolf
8b0719d1e3
Improvements in sf2 cells_sim.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 16:18:49 -08:00
Clifford Wolf
2d2c1617ee
Add sf2 techmap rules for more FF types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 15:47:54 -08:00
Clifford Wolf
78762316aa
Refactor SF2 iobuf insertion, Add clkint insertion
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-06 00:41:02 -08:00
Clifford Wolf
da5181a3df
Improvements in SF2 flow and demo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 20:36:00 -08:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream
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Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
Clifford Wolf
724576a4e2
Merge pull request #850 from daveshah1/ecp5_warn_conflict
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ecp5: Demote conflicting FF init values to a warning
2019-03-05 15:23:01 -08:00
Clifford Wolf
13844c7658
Use "write_edif -pvector bra" for Xilinx EDIF files
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-05 15:16:13 -08:00
Keith Rothman
228f132ec3
Revert BRAM WRITE_MODE changes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-04 09:22:22 -08:00
David Shah
777864d02e
ecp5: Demote conflicting FF init values to a warning
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 11:26:20 +00:00
Keith Rothman
3e16f75bc6
Revert FF models to include IS_x_INVERTED parameters.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb
Use singular for disabling of DRAM or BRAM inference.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8
Modify arguments to match existing style.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54
Changes required for VPR place and route synth_xilinx.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 12:02:27 -08:00
Miodrag Milanovic
ca2b3feed8
Fix ECP5 cells_sim for iverilog
2019-03-01 19:25:23 +01:00
Clifford Wolf
a82a7eb42e
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 20:27:27 -08:00
Elms
cd2902ab1f
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
2019-02-28 16:23:40 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve
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ECP5 Improvements
2019-02-28 14:46:56 -08:00
Eddie Hung
1da0909662
Remove SRL16/32 from cells_xtra
2019-02-28 13:56:45 -08:00
Eddie Hung
73ddab6960
Add SRL16 and SRL32 sim models
2019-02-28 13:56:22 -08:00
Eddie Hung
8aab7fe7e6
Fix SRL16/32 techmap off-by-one
2019-02-28 13:56:00 -08:00
Eddie Hung
fe4d6898de
synth_xilinx to call shregmap with enable support
2019-02-28 11:17:13 -08:00
Eddie Hung
68f38f2ee0
synth_xilinx to use shregmap with -params too
2019-02-28 10:21:05 -08:00
Eddie Hung
c9ab18889a
synth_xilinx to now have shregmap call after dff2dffe
2019-02-28 09:32:29 -08:00
Eddie Hung
c29f0c5048
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
2019-02-28 09:31:24 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Larry Doolittle
7a40294e93
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
David Shah
fa2f595cfa
ecp5: Compatibility with Migen AsyncResetSynchronizer
...
Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-25 13:24:30 +00:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
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Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Eddie Hung
a8803a1519
Merge remote-tracking branch 'origin/master' into xaig
2019-02-21 11:23:00 -08:00
Clifford Wolf
2fe1c830eb
Bugfix in ice40_dsp
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung
45ddd9066e
synth to take -abc9 argument
2019-02-20 11:08:49 -08:00
Clifford Wolf
84999a7e68
Add ice40 test_dsp_map test case generator
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb
Add "synth_ice40 -dsp"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
7bf4e4a185
Improve iCE40 SB_MAC16 model
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 12:55:20 +01:00
Eddie Hung
f9af902532
Merge branch 'master' into xaig
2019-02-19 14:20:04 -08:00
David Shah
bb56cb738d
ecp5: Add DDRDLLA
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 19:34:37 +00:00
David Shah
c36f15b489
ecp5: Add DELAYF/DELAYG blackboxes
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 14:10:43 +00:00
Clifford Wolf
62493c91b2
Add first draft of functional SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-19 14:47:27 +01:00
Eddie Hung
323dd0e608
synth_ice40 to have new -abc9 arg
2019-02-14 13:19:27 -08:00
David Shah
e0bc190879
ecp5: Add ECLKSYNCB blackbox
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-13 11:23:25 +00:00
David Shah
7913baedd8
ecp5: Full set of IO-related blackboxes
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Signed-off-by: David Shah <dave@ds0.me>
2019-02-12 12:04:41 +00:00
Eddie Hung
e8f4dc739c
Cope WIDTH of ff/latch cells is default of zero
2019-02-06 15:51:12 -08:00
Eddie Hung
742b4e01b4
Add INIT parameter to all ff/latch cells
2019-02-06 14:16:26 -08:00
David Shah
95789c6136
ecp5: Use abc -dress
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
David Shah
7ef2333497
ice40: Use abc -dress in synth_ice40
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
Miodrag Milanovic
0de328da8f
Fixed Anlogic simulation model
2019-01-25 19:25:25 +01:00
David Shah
549b8e74b2
ecp5: Support for flipflop initialisation
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-22 16:02:56 +00:00
David Shah
ee8c9e854f
ecp5: Add LSRMODE to flipflops for PRLD support
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:35:22 +00:00
David Shah
d8003e87d1
ecp5: More blackboxes
...
Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:34:34 +00:00
David Shah
01ea72f53a
ecp5: Increase threshold for ALU mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-01-21 12:33:47 +00:00
Clifford Wolf
db5765b443
Add SF2 IO buffer insertion
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 14:38:37 +01:00
Clifford Wolf
841ca74c90
Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 13:33:45 +01:00
Clifford Wolf
e041ae3c6d
Merge pull request #777 from mmicko/achronix_cell_sim_fix
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Fix cells_sim.v for Achronix FPGA
2019-01-04 15:18:18 +01:00
Miodrag Milanovic
50ef4561d4
Fix cells_sim.v for Achronix FPGA
2019-01-04 15:15:23 +01:00
Miodrag Milanovic
3b17c9018a
Unify usage of noflatten among architectures
2019-01-04 11:37:25 +01:00
Clifford Wolf
56ca1e6afc
Merge pull request #755 from Icenowy/anlogic-dram-init
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anlogic: implement DRAM initialization
2019-01-02 16:28:18 +01:00
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init
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Initialization of Anlogic DFFs
2019-01-02 15:52:22 +01:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut
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synth: add k-LUT mode
2019-01-02 15:44:57 +01:00
Clifford Wolf
00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut
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cmp2lut: new techmap pass
2019-01-02 15:43:10 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
17b2831356
synth_ice40: use 4-LUT coarse synthesis mode.
2019-01-02 08:25:55 +00:00
whitequark
18174202a9
synth: add k-LUT mode.
2019-01-02 08:25:03 +00:00
whitequark
fdff32dd73
synth: improve script documentation. NFC.
2019-01-02 08:05:44 +00:00
whitequark
a91892bba4
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
Clifford Wolf
e09e49ca54
Merge pull request #766 from Icenowy/anlogic-latches
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anlogic: add latch cells
2018-12-31 15:52:01 +01:00
Larry Doolittle
ebe9351f82
Fix 7 instances of add_share_file to add_gen_share_file
...
in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
2018-12-29 12:53:12 +01:00
Icenowy Zheng
1b36944299
anlogic: add latch cells
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Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-25 22:47:46 +08:00
Icenowy Zheng
90d00182cf
anlogic: implement DRAM initialization
...
As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.
Now add the support by add a new pass to determine unknown values in the
initial value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-20 07:56:15 +08:00
Clifford Wolf
93d44bb9a6
Merge pull request #752 from Icenowy/anlogic-lut-cost
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Anlogic: let LUT5/6 have more cost than LUT4-
2018-12-19 19:52:31 +01:00
Clifford Wolf
c98d44ac12
Merge pull request #753 from Icenowy/anlogic-makefile-fix
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anlogic: fix Makefile.inc
2018-12-19 19:51:10 +01:00
Icenowy Zheng
3993ba71f7
anlogic: fix Makefile.inc
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During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.
Fix this issue.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 10:23:58 +08:00
Icenowy Zheng
c9513c695a
Anlogic: let LUT5/6 have more cost than LUT4-
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According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.
So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.
Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 09:36:53 +08:00
Icenowy Zheng
4bf8ac728c
anlogic: set the init value of DFFs
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As dffinit has already supported for different initialization strings
for DFFs and check for re-initialization, initialization of Anlogic
DFFs are now ready to go.
Support for set the init values of Anlogic DFFs.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:16:37 +08:00
Icenowy Zheng
7854d5ba21
anlogic: fix dbits of Anlogic Eagle DRAM16X4
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The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.
Fix the dbits number in the RAM configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 14:38:44 +08:00
Icenowy Zheng
d53a2bd1d3
anlogic: add support for Eagle Distributed RAM
...
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.
Enable to synthesis to DRAM.
As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Icenowy Zheng
634d7d1c14
Revert "Leave only real black box cells"
...
This reverts commit 43030db5ff
.
For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
Clifford Wolf
5fa5dbbdda
Rename "fine:" label to "map:" in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 16:36:19 +01:00
Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf
ceffa66dbd
Merge pull request #730 from smunaut/ffssr_dont_touch
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ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-16 15:50:42 +01:00
Clifford Wolf
0c69f1d777
Merge pull request #725 from olofk/ram4k-init
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Only use non-blocking assignments of SB_RAM40_4K for yosys
2018-12-16 15:42:04 +01:00
Sylvain Munaut
add6ab9b2a
ice40: Honor the "dont_touch" attribute in FFSSR pass
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This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-08 22:46:28 +01:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
Olof Kindgren
889297c62a
Only use non-blocking assignments of SB_RAM40_4K for yosys
...
In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.
Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.
This patch will change to use non-blocking assignments only for yosys
2018-12-06 21:45:59 +01:00
whitequark
6e559ee3c7
synth_ice40: split `map_gates` off `fine`.
2018-12-06 12:04:39 +00:00
whitequark
d9fa4387c9
synth_ice40: add -noabc option, to use built-in LUT techmapping.
...
This should be combined with -relut to get sensible results.
2018-12-05 17:13:46 +00:00
whitequark
9ef078848a
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
whitequark
12596b5003
Fix typo.
2018-12-05 17:13:27 +00:00
Clifford Wolf
e115303129
Merge pull request #713 from Diego-HR/master
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Changes in GoWin synth commands and ALU primitive support
2018-12-05 09:08:30 -08:00
Clifford Wolf
1a260ce89b
Merge pull request #712 from mmicko/anlogic-support
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Initial support for Anlogic FPGA
2018-12-05 09:08:04 -08:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
ea4870b126
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
2018-12-05 16:30:37 +00:00
whitequark
1719aa88ac
Extract ice40_unlut pass from ice40_opt.
...
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
2018-12-05 16:30:24 +00:00
Diego H
819ca73096
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
Miodrag Milanovic
43030db5ff
Leave only real black box cells
2018-12-02 11:57:50 +01:00
Miodrag Milanovic
83bce9f59c
Initial support for Anlogic FPGA
2018-12-01 18:28:54 +01:00
Sylvain Munaut
3e5ab50a73
ice40: Add option to only use CE if it'd be use by more than X FFs
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
dbc4cb8f4a
Merge pull request #697 from eddiehung/xilinx_ps7
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Add support for PS7 block for Xilinx
2018-11-12 09:09:22 +01:00
Clifford Wolf
317cc9c2b7
Merge pull request #695 from daveshah1/ecp5_bb
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ecp5: Adding some blackbox cells
2018-11-12 09:08:49 +01:00
Eddie Hung
99a14b0e37
Add support for Xilinx PS7 block
2018-11-10 12:45:07 -08:00
David Shah
fae3e645a2
ecp5: Add 'fake' DCU parameters
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-09 18:25:42 +00:00
David Shah
960c8794fa
ecp5: Add blackboxes for ancillary DCU cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-09 15:18:30 +00:00
David Shah
1f51332808
ecp5: Adding some blackbox cells
...
Signed-off-by: David Shah <dave@ds0.me>
2018-11-07 14:56:38 +00:00
Clifford Wolf
d084fb4c3f
Fix sf2 LUT interface
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-31 15:36:53 +01:00
Clifford Wolf
cf79fd4376
Basic SmartFusion2 and IGLOO2 synthesis support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-31 15:28:57 +01:00
David Shah
b65932edc4
ecp5: Remove DSP parameters that don't work
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-22 16:20:38 +01:00
David Shah
101f5234ff
ecp5: Add DSP blackboxes
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-21 19:27:02 +01:00
David Shah
d29b517fef
ecp5: Sim model fixes
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 15:16:40 +01:00
David Shah
677b8ed3ca
ecp5: Add latch inference
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-19 15:16:40 +01:00
Clifford Wolf
24a5c65856
Merge pull request #657 from mithro/xilinx-vpr
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xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
2018-10-18 10:54:03 +02:00
David Shah
df4bfa0ad6
ecp5: Disable LSR inversion
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-16 12:48:39 +01:00
David Shah
812538a036
BRAM improvements
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-12 14:22:21 +01:00
David Shah
bdfead8c64
ecp5: Adding BRAM maps for all size options
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 17:18:17 +01:00
David Shah
983fb7ff88
ecp5: First BRAM type maps successfully
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 16:35:19 +01:00
David Shah
2ef1af8b58
ecp5: Script for BRAM IO connections
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-10 16:11:00 +01:00
David Shah
346cbbdbdc
ecp5: Adding BRAM initialisation and config
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell
b111ea1228
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
...
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
2018-10-08 16:52:12 -07:00
David Shah
31e22c8b96
ecp5: Add blackbox for DP16KD
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-05 11:35:59 +01:00
Clifford Wolf
5f1fea08d5
Add inout ports to cells_xtra.v
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-04 11:30:55 +02:00
Tim Ansell
ad975fb694
xilinx: Adding missing inout IO port to IOBUF
2018-10-03 16:38:32 -07:00
Clifford Wolf
76baae4b94
Merge pull request #645 from daveshah1/ecp5_dram_fix
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ecp5: Don't map ROMs to DRAM
2018-10-02 10:00:10 +02:00
David Shah
fcd39e1398
ecp5: Don't map ROMs to DRAM
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-10-01 18:34:41 +01:00
Clifford Wolf
51f1bbeeb0
Add iCE40 SB_SPRAM256KA simulation model
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-10 11:57:24 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
David Shah
3a3558acce
ecp5: Fixing miscellaneous sim model issues
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:56:12 +02:00
David Shah
e9ef077266
ecp5: Fixing 'X' issues with LUT simulation models
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 15:20:34 +02:00
David Shah
b2c62ff8ef
ecp5: ECP5 synthesis fixes
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-16 14:33:13 +02:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
David Shah
241429abac
ecp5: Add DRAM match rule
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:25:52 +02:00
David Shah
4a60bc83ab
ecp5: Cells and mappings fixes
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 16:14:08 +02:00
David Shah
b0fea67cc6
ecp5: Fixing arith_map
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:49:59 +02:00
David Shah
11c916840d
ecp5: Initial arith_map implementation
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 15:46:12 +02:00
David Shah
c2d7be140a
ecp5: Adding basic synth_ecp5 based on synth_ice40
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:52:25 +02:00
David Shah
eb8f3f7dc4
ecp5: Adding DFF maps
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:32:23 +02:00
David Shah
1def34f2a6
ecp5: Adding DRAM map
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 14:08:42 +02:00
David Shah
b1b9e23f94
ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:27:24 +02:00
David Shah
cd65eeb3b3
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:09:18 +02:00
Clifford Wolf
57fc8dd582
Add "synth_ice40 -json"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-13 13:35:10 +02:00
Clifford Wolf
83631555dd
Fix ice40_opt for cases where a port is connected to a signal with width != 1
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-11 18:12:42 +02:00
Clifford Wolf
7fecc3c199
Make -nordff the default in "prep"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 13:17:09 +02:00
Olof Kindgren
faac2c5595
Avoid mixing module port declaration styles in ice40 cells_sim.v
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The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
2018-05-17 13:54:43 +02:00
Clifford Wolf
47eb150eec
Merge pull request #537 from mithro/yosys-vpr
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Improving Yosys when used with VPR
2018-05-04 12:32:30 +02:00
Clifford Wolf
b4c1d3084f
Add "synth_intel --noiopads"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-30 13:02:56 +02:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
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* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Tim 'mithro' Ansell
ca39e493ba
synth_ice40: Rework the vpr blif output slightly.
2018-04-18 16:55:08 -07:00
Clifford Wolf
81a457c4a6
Add "synth_ice40 -nodffe"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-16 20:44:26 +02:00
c60k28
efed2420d6
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
Robert Ou
14e49fb057
coolrunner2: Add an ANDTERM/XOR between chained FFs
...
In some cases (e.g. the low bits of counters) the design might end up
with a flip-flop whose input is directly driven by another flip-flop.
This isn't possible in the Coolrunner-II architecture, so add a single
AND term and XOR in this case.
2018-03-31 03:54:48 -07:00
Robert Ou
cfa3753b89
coolrunner2: Split multi-bit nets
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The PAR tool doesn't expect any "dangling" nets with no drivers nor
sinks. By splitting the nets, clean removes them.
2018-03-31 02:56:11 -07:00
Robert Ou
8fe9cdf364
coolrunner2: Add extraction for TFFs
2018-03-31 02:54:26 -07:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
Clifford Wolf
6991c132b5
Add Xilinx RAM64X1D and RAM128X1D simulation models
2018-03-07 17:31:48 +01:00
Clifford Wolf
27dd500d31
Add "synth -noshare"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 17:13:45 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Robert Ou
2abcd98527
coolrunner2: Move LOC attributes onto the IO cells
2018-01-17 16:17:32 -08:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
b66d50e62d
Fix minor typo in "prep" help message
2017-12-19 21:44:05 +01:00
Graham Edgecombe
f93e6637aa
Fix port names in SB_IO_OD
2017-12-10 15:33:38 +00:00
Graham Edgecombe
52ace35a73
Remove trailing comma from SB_IO_OD port list
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This isn't compatible with Icarus Verilog.
2017-12-10 15:33:38 +00:00
Tim Ansell
3cc31f197c
Fix spelling in -vpr help for synth_ice40
2017-12-08 18:44:45 -08:00
Clifford Wolf
1f6e8f86c5
Merge pull request #462 from daveshah1/up5k
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Add remaining UltraPlus cells to ice40 techlib
2017-11-28 15:53:53 +01:00
David Shah
5e8d1922a4
Add remaining UltraPlus cells to ice40 techlib
2017-11-28 11:07:49 +00:00
Clifford Wolf
4782d59a3f
Merge pull request #455 from daveshah1/up5k
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Add UltraPlus specific cells to ice40 techlib
2017-11-18 19:12:48 +01:00
David Shah
0505f1043c
Remove unnecessary keep attributes
2017-11-18 17:53:21 +00:00
Clifford Wolf
c01df04e32
Merge pull request #453 from dh73/master
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Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
2017-11-18 09:56:36 +01:00
David Shah
8ae73e60e2
Merge branch 'master' into up5k
2017-11-17 15:15:39 +00:00
Clifford Wolf
234726c655
Add "synth_ice40 -vpr"
2017-11-16 21:37:02 +01:00
David Shah
f9f3ca5da0
Add some UltraPlus cells to ice40 techlib
2017-11-16 12:24:35 +00:00
dh73
3fd1d61e2a
Initial Cyclone 10 support
2017-11-08 22:45:21 -06:00
dh73
1fc061d90c
Organizing Speedster file names
2017-11-08 20:23:55 -06:00
Larry Doolittle
50bcd9a728
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
Clifford Wolf
65f91e5120
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
2017-10-03 17:31:21 +02:00
dh73
4718e65763
Tested and working altsyncarm without init files
2017-10-01 19:59:45 -05:00
dh73
cbaba62401
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00
Clifford Wolf
c5b204d8d2
Add first draft of eASIC back-end
2017-09-29 17:53:43 +02:00
Clifford Wolf
e64b9d5a4d
Fix synth_ice40 doc regarding -top default
2017-09-29 17:52:57 +02:00
Andrew Zonenberg
122532b7e1
Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.
2017-09-14 10:26:32 -07:00
Andrew Zonenberg
a84172b23b
Initial support for extraction of counters with clock enable
2017-09-14 10:26:10 -07:00
Clifford Wolf
2f75240e36
Merge pull request #406 from azonenberg/coolrunner-techmap
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Coolrunner techmapping improvements
2017-09-02 13:43:51 +02:00
Robert Ou
5f65e24ccb
coolrunner2: Finish fixing special-use p-terms
2017-09-01 07:22:16 -07:00
Robert Ou
fa04366f38
coolrunner2: Generate a feed-through AND term when necessary
2017-09-01 07:22:01 -07:00
Robert Ou
6775177171
coolrunner2: Initial fixes for special p-terms
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Certain signals can only be controlled by a product term and not a
sum-of-products. Do the initial work for fixing this.
2017-09-01 07:21:51 -07:00
Robert Ou
7f08be4304
coolrunner2: Fix mapping of flip-flops
2017-09-01 07:21:39 -07:00
Robert Ou
ac84f47829
coolrunner2: Combine some for loops together
2017-09-01 07:21:31 -07:00
Andrew Zonenberg
40021d2fd8
Fixed typo in error message
2017-09-01 06:45:10 -07:00
Andrew Zonenberg
fc0c7f74dc
Added blackbox $__COUNT_ cell model
2017-09-01 06:44:28 -07:00
Andrew Zonenberg
80aaf50302
Refactoring: moved modules still in cells_sim to cells_sim_wip
2017-09-01 06:44:15 -07:00
Andrew Zonenberg
06754108fc
Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-extraction
2017-08-30 16:40:41 -07:00
Andrew Zonenberg
634f18be96
extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
2017-08-30 16:28:25 -07:00
Andrew Zonenberg
3fc1b9f3fd
Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells.
2017-08-28 22:18:57 -07:00
Andrew Zonenberg
b5c15636c5
Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass
2017-08-28 22:18:34 -07:00
Andrew Zonenberg
c3145863e7
Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused.
2017-08-28 14:25:46 -07:00
Andrew Zonenberg
e62362225c
Fixed bug causing GP_SPI model to not synthesize
2017-08-27 07:31:48 -07:00
Andrew Zonenberg
e6eaf487b6
Fixed more issues with GreenPAK counter sim models
2017-08-15 09:18:36 -07:00
Andrew Zonenberg
3a404be62a
Updated PGEN model to have level triggered reset (matches actual hardware behavior
2017-08-15 09:18:27 -07:00
Andrew Zonenberg
e5109847c9
Fixed bug in GP_COUNTx model
2017-08-15 09:18:17 -07:00
Andrew Zonenberg
66b256d40e
Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high
2017-08-15 09:18:07 -07:00
Clifford Wolf
2cf0b5c157
Merge pull request #381 from azonenberg/countfix
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Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
2017-08-14 21:47:26 +02:00
Robert Ou
78fd24f40f
coolrunner2: Add INVERT parameter to some BUFGs
2017-08-14 12:13:33 -07:00
Robert Ou
1e3ffd57cb
coolrunner2: Add FFs with clock enable to cells_sim.v
2017-08-14 12:13:25 -07:00
Andrew Zonenberg
348acbd968
Fixed typo in GP_COUNT8 sim model
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
c205d571df
Fixed typo in error message
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
0a6c702c41
Changed LEVEL resets for GP_COUNTx to be properly synthesizeable
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
9f3dc59ffe
Changed LEVEL resets to be edge triggered anyway
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
b049ead042
Added level-triggered reset support to GP_COUNTx simulation models
2017-08-14 10:45:40 -07:00
Andrew Zonenberg
ac75524f69
Fixed undeclared "count" in GP_COUNT8_ADV
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
db20e3f1c2
Fixed undeclared "count" in GP_COUNT14_ADV
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
3618ca2218
Fixed typo in last commit
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
4da1a327c0
Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else.
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
4504dd78e9
Fixed typo in COUNT8 model
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
60dd5dba7b
Moved GP_POR out of digital cells b/c it has delays
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
f55d4cc2fd
Improved cells_sim_digital model for GP_COUNT8
2017-08-14 10:45:39 -07:00
Andrew Zonenberg
fe3a932cfa
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
2017-08-14 10:45:39 -07:00
Clifford Wolf
8a69759306
Add techlibs/xilinx/lut2lut.v
2017-07-10 12:09:05 +02:00
Clifford Wolf
621787a9e0
Fix some c++ clang compiler errors
2017-07-03 19:38:30 +02:00
Clifford Wolf
5c1c126374
Apply minor coding style changes to coolrunner2 target
2017-07-03 19:35:40 +02:00
Clifford Wolf
6afee022ad
Merge pull request #352 from rqou/master
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Initial Coolrunner-II support
2017-07-03 19:33:36 +02:00
Robert Ou
b102c0e254
coolrunner2: Add a few more primitives
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These cannot be inferred yet, but add them to cells_sim.v for now
2017-06-25 23:58:28 -07:00
Robert Ou
36b75dfcb7
coolrunner2: Initial mapping of latches
2017-06-25 23:58:28 -07:00
Robert Ou
4af5baab21
coolrunner2: Initial mapping of DFFs
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All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
2017-06-25 23:58:28 -07:00
Robert Ou
1eb5dee799
coolrunner2: Remove redundant INVERT_PTC
2017-06-25 23:58:28 -07:00
Robert Ou
ffff001008
coolrunner2: Remove debug prints
2017-06-25 23:58:28 -07:00
Robert Ou
5798105d47
coolrunner2: Correctly handle $_NOT_ after $sop
2017-06-25 23:58:28 -07:00
Robert Ou
908ce3fdce
coolrunner2: Also construct the XOR cell in the macrocell
2017-06-25 23:58:28 -07:00
Robert Ou
a64b56648d
coolrunner2: Initial techmapping for $sop
2017-06-25 23:58:22 -07:00
Andrew Zonenberg
cbdddc3af9
greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
2017-06-24 14:54:07 -07:00
Robert Ou
6e0fb889fa
coolrunner2: Initial commit
2017-06-24 07:22:56 -07:00
Clifford Wolf
e7a984a4df
Add dff2ff.v techmap file
2017-05-31 11:45:58 +02:00
Andrew Zonenberg
184bd148c9
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
2017-05-22 19:39:55 -07:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
dh73
c27dcc1e47
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00
Clifford Wolf
f3324ed0cc
Merge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 13:08:27 +01:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Andrew Zonenberg
6fed2dc996
Merge https://github.com/cliffordwolf/yosys
2017-02-14 08:29:37 -08:00
Clifford Wolf
2a311c2c38
Fix double-call of log_pop() in synth_greenpak4
2017-02-14 11:57:54 +01:00
Andrew Zonenberg
0d7e71f7ab
Merge https://github.com/cliffordwolf/yosys
2017-02-08 22:12:29 -08:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Andrew Zonenberg
27a626ce98
greenpak4: Added POUT to GP_COUNTx cells
2017-01-01 00:56:20 -08:00
Andrew Zonenberg
ada98844b9
greenpak4: Added INT pin to GP_SPI
2016-12-21 11:35:29 +08:00
Andrew Zonenberg
6b526e9382
greenpak4: removed unused MISO pin from GP_SPI
2016-12-21 11:33:32 +08:00
Andrew Zonenberg
638f3e3b12
greenpak4: Removed SPI_BUFFER parameter
2016-12-20 13:07:49 +08:00
Andrew Zonenberg
073e8df9f1
greenpak4: replaced MOSI/MISO with single one-way SDAT pin
2016-12-20 12:34:56 +08:00
Andrew Zonenberg
d4a05b499e
greenpak4: Changed port names on GP_SPI for clarity
2016-12-20 10:30:38 +08:00
Andrew Zonenberg
eb80ec84aa
greenpak4: Initial implementation of GP_SPI cell
2016-12-20 09:58:02 +08:00
Andrew Zonenberg
de1d81511a
greenpak4: Updated GP_DCMP cell model
2016-12-17 12:01:22 +08:00
Andrew Zonenberg
7cdba8432c
greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
2016-12-16 15:14:20 +08:00
Andrew Zonenberg
bea6e2f11f
greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX
2016-12-15 15:19:35 +08:00
Andrew Zonenberg
3690aa556c
greenpak4: More fixups of GP_DCMPx cells
2016-12-15 07:19:08 +08:00
Andrew Zonenberg
3491d33863
greenpak4: And another typo :(
2016-12-15 07:17:07 +08:00
Andrew Zonenberg
ea787e6be3
greenpak4: Fixed another typo
2016-12-15 07:16:26 +08:00
Andrew Zonenberg
58da621ac3
greenpak4: Fixed typo
2016-12-15 07:15:38 +08:00
Andrew Zonenberg
262f8f913c
greenpak4: Cleaned up trailing spaces in cells_sim
2016-12-14 14:14:45 +08:00
Andrew Zonenberg
c77e6e6114
greenpak4: Added GP_DCMPREF / GP_DCMPMUX
2016-12-14 14:14:26 +08:00
Andrew Zonenberg
c3c2983d12
Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
2016-12-11 10:04:00 +08:00
Andrew Zonenberg
8f3d1f8fcf
greenpak4: Added support for inferred input/output inverters on latches
2016-12-10 19:58:32 +08:00
Andrew Zonenberg
c53a33143e
greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)
2016-12-10 18:46:36 +08:00
Andrew Zonenberg
797c03997e
greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency
2016-12-10 13:57:37 +08:00
Andrew Zonenberg
8767cdcac9
Added GP_DLATCH and GP_DLATCHI
2016-12-05 23:49:06 -08:00
Andrew Zonenberg
981f014301
Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.
2016-12-05 21:22:41 -08:00
Andrew Zonenberg
e6ab00d419
Updated help text for synth_greenpak4
2016-12-05 20:11:37 -08:00
Clifford Wolf
e9d73d2ee0
Indenting fixes in gowin sim cell lib
2016-11-08 18:54:00 +01:00
Clifford Wolf
3db2ac4e00
Added hex constant support to write_verilog
2016-11-03 12:13:23 +01:00
Clifford Wolf
81bdf0ad0f
iCE40 flow is not experimental anymore
2016-11-01 11:32:02 +01:00
Clifford Wolf
cae5131bac
Added initial version of "synth_gowin"
2016-11-01 11:31:13 +01:00
Andrew Zonenberg
1cca1563c6
Fixed typo in last commit
2016-10-18 20:46:49 -07:00
Andrew Zonenberg
e78fa157a3
greenpak4: Added GP_PGEN cell definition
2016-10-18 20:42:44 -07:00
Andrew Zonenberg
091d32b563
Added GLITCH_FILTER parameter to GP_DELAY
2016-10-18 19:53:19 -07:00
Andrew Zonenberg
a818472f0c
greenpak4: added model for GP_EDGEDET block
2016-10-18 19:33:26 -07:00
Andrew Zonenberg
d6feb4b43e
greenpak4: Changed parameters for GP_SYSRESET
2016-10-16 22:53:43 -07:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
76352c99c9
Added "prep -nokeepdc"
2016-09-30 17:02:52 +02:00
Clifford Wolf
2ee9bf10d0
Added "prep -nomem"
2016-08-30 23:57:24 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
d77a914683
Added "wreduce -memx"
2016-08-20 12:52:50 +02:00
Clifford Wolf
15ef608453
Added memory_memx pass, "memory -memx", and "prep -memx"
2016-08-19 19:48:26 +02:00
Clifford Wolf
5d90a5b905
Added greenpak4_dffinv
2016-08-15 09:33:06 +02:00
Andrew Zonenberg
0b0ba96488
greenpak4: Changed name of inverted output ports for consistency
2016-08-14 00:30:45 -07:00
Andrew Zonenberg
3b9756c6a3
greenpak4: Added GP_DFFxI cells
2016-08-14 00:11:44 -07:00
Andrew Zonenberg
2b062c48cb
greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)
2016-08-13 22:27:58 -07:00
whitequark
0515809448
synth_greenpak4: use attrmvcp to move LOC from wires to cells.
2016-08-10 20:09:35 +00:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Andrew Zonenberg
52a738a544
Added GP_DAC cell
2016-07-11 22:45:55 -07:00
Andrew Zonenberg
baae472b83
Removed VOUT port of GP_BANDGAP
2016-07-11 22:45:42 -07:00
Andrew Zonenberg
8619d33114
Removed splitnets in prep for new gp4par parser
2016-07-11 22:42:25 -07:00
Clifford Wolf
cdb58f68ab
Added "prep -auto-top" and "synth -auto-top"
2016-07-11 11:40:55 +02:00
whitequark
c0645839fe
greenpak4: add GP_COUNT{8,14}_ADV cells.
2016-07-10 15:46:46 +00:00
Clifford Wolf
21659847a7
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
2016-07-08 14:41:36 +02:00
Clifford Wolf
df5ebfa0a0
Improved ice40_ffinit error reporting
2016-06-30 09:58:13 +02:00
Clifford Wolf
ca91bccb6b
Added "deminout"
2016-06-19 13:08:16 +02:00
Clifford Wolf
95757efb25
Improved support for $sop cells
2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
99edf24966
Added "nlutmap -assert"
2016-06-09 11:47:41 +02:00
Clifford Wolf
52b0b4e31e
Do not run "wreduce" in "prep -ifx"
2016-06-08 12:14:32 +02:00
Clifford Wolf
2032e6d8e4
Added "proc_mux -ifx"
2016-06-06 17:15:50 +02:00
Andrew Zonenberg
47eace0b9f
Added GP_DELAY cell
2016-05-07 21:29:26 -07:00
Andrew Zonenberg
41bbad4e4c
Fixed typo in port name
2016-05-07 21:14:42 -07:00
Andrew Zonenberg
b5171541cd
Fixed extra semicolon
2016-05-07 21:14:18 -07:00
Andrew Zonenberg
85ee88b0ee
Fixed typo in parameter name
2016-05-07 21:14:00 -07:00
Andrew Zonenberg
a0c19aae55
Added simulation timescale declaration
2016-05-07 21:13:47 -07:00
Clifford Wolf
6fe3d5a1cf
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Clifford Wolf
126da0ad3d
Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
2016-05-06 14:32:32 +02:00
Andrew Zonenberg
2096a05ec2
Changed order of passes for better handling of INIT attributes on "output reg" FFs
2016-05-04 17:13:54 -07:00
Andrew Zonenberg
dee1c27a19
Renamed module parameter
2016-05-04 17:03:45 -07:00
Andrew Zonenberg
a613f171ae
Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract
2016-05-04 15:55:16 -07:00
Andrew Zonenberg
deb1eccab5
Fixed incorrect signal naming in GP_IOBUF
2016-05-04 08:06:18 -07:00
Andrew Zonenberg
dcee3256d5
Added tri-state I/O extraction for GreenPak
2016-05-03 22:53:29 -07:00
Andrew Zonenberg
66095153fd
Added GreenPak I/O buffer cells
2016-05-03 22:03:04 -07:00
Andrew Zonenberg
9fc9d5f1fb
Added comment to clarify GP_ABUF cell
2016-05-02 20:29:39 -07:00
Andrew Zonenberg
79460208c9
Added GP_ABUF cell
2016-05-02 20:27:41 -07:00
Andrew Zonenberg
134e093e4e
Added GP_PGA cell
2016-04-27 23:07:21 -07:00
Andrew Zonenberg
d57c85111f
Merge https://github.com/cliffordwolf/yosys
2016-04-24 22:11:56 -07:00
Andrew Zonenberg
349d717202
Removed VIN_BUF_EN
2016-04-24 17:01:21 -07:00
Andrew Zonenberg
6e215f374d
Renamed VOUT to OUT on GP_ACMP cell
2016-04-23 22:53:49 -07:00
Andrew Zonenberg
512486dcf3
Added GP_ACMP cell
2016-04-23 22:33:36 -07:00
Clifford Wolf
09ffebb995
Added "prep -flatten" and "synth -flatten"
2016-04-24 00:48:33 +02:00
Clifford Wolf
77aa2031e7
Converted "prep" to ScriptPass
2016-04-24 00:48:06 +02:00
Clifford Wolf
c9c5192cd6
Run clean after splitnets in synth_greenpak4
2016-04-23 23:09:45 +02:00
Clifford Wolf
34195f281f
Merge https://github.com/azonenberg/yosys
2016-04-23 10:33:32 +02:00
Clifford Wolf
f85cfa5666
Added "shregmap" to synth_greenpak4
2016-04-23 10:31:19 +02:00
Clifford Wolf
a24021ea20
Converted synth_greenpak4 to ScriptPass
2016-04-23 10:27:33 +02:00
Andrew Zonenberg
0cbe70eaa4
Fixed typo
2016-04-22 19:08:19 -07:00
Andrew Zonenberg
ab11f2aa70
Merge https://github.com/cliffordwolf/yosys
2016-04-22 19:07:55 -07:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Andrew Zonenberg
d90c1e9522
Added GP_VREF cell
2016-04-20 20:48:19 -07:00
Andrew Zonenberg
d0aaf8d262
Added GP_SHREG cell
2016-04-13 23:13:51 -07:00
Andrew Zonenberg
cdefa60367
Refactoring: alphabetized cells_sim
2016-04-13 23:13:39 -07:00
Andrew Zonenberg
f1679936fe
Fixed missing semicolon
2016-04-09 01:18:02 -07:00
Andrew Zonenberg
58d8715681
Added GP_RCOSC cell
2016-04-09 01:17:13 -07:00
Andrew Zonenberg
01a5f71187
Fixed assertion failure for non-inferrable counters in some cases
2016-04-06 23:42:22 -07:00
Andrew Zonenberg
48c10d90f4
Added second divider to GP_RINGOSC
2016-04-06 23:10:34 -07:00
Andrew Zonenberg
1df559c706
Added GP_RINGOSC primitive
2016-04-06 22:40:25 -07:00
Andrew Zonenberg
c2b909c051
Added GP_POR
2016-04-04 21:46:07 -07:00
Andrew Zonenberg
c01ff05fab
Added GP_BANDGAP cell
2016-04-04 16:56:43 -07:00
Andrew Zonenberg
34667ded53
Removed more debug prints
2016-04-01 23:41:03 -07:00
Andrew Zonenberg
87e7cd9fbd
Removed forgotten debug code
2016-04-01 23:39:32 -07:00
Andrew Zonenberg
2386885f22
Added GreenPak inverter support
2016-04-01 21:18:29 -07:00
Andrew Zonenberg
6dbcf50fa1
Added support for inferring counters with asynchronous resets. Fixed use-after-free in inference pass.
2016-04-01 18:07:59 -07:00
Andrew Zonenberg
f277267916
Merge https://github.com/cliffordwolf/yosys
2016-04-01 00:03:00 -07:00
Andrew Zonenberg
736a998a75
DFFINIT is now correctly called for all kinds of flipflop, not just DFF
2016-03-31 23:16:45 -07:00
Andrew Zonenberg
7498ff8041
Fixed incorrect port name in cells_map.v
2016-03-31 22:51:22 -07:00
Clifford Wolf
2553319081
Added ScriptPass helper class for script-like passes
2016-03-31 11:16:34 +02:00
Andrew Zonenberg
c04a3d2763
Fixed typo (wasn't written in 2012)
2016-03-30 23:58:45 -07:00
Clifford Wolf
ec93680bd5
Renamed opt_share to opt_merge
2016-03-31 08:52:49 +02:00
Clifford Wolf
1d0f0d668a
Renamed opt_const to opt_expr
2016-03-31 08:46:56 +02:00
Clifford Wolf
d31c968d76
Fixed typo in greenpak4_counters.cc
2016-03-31 08:00:59 +02:00
Andrew Zonenberg
984561c034
Renamed counters pass to greenpak4_counters
2016-03-30 22:52:01 -07:00
Andrew Zonenberg
1ae33344f4
Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now.
2016-03-30 22:40:14 -07:00
Andrew Zonenberg
94a6923e7d
Updated tech lib for greenpak4 counter with some clarifications
2016-03-30 20:30:25 -07:00
Andrew Zonenberg
489caf32c5
Initial work on greenpak4 counter extraction. Doesn't work but a decent start
2016-03-30 01:07:20 -07:00
Andrew Zonenberg
3ea6026648
Added splitnets to synth_greenpak4
2016-03-29 20:02:59 -07:00
Clifford Wolf
19c20235b5
Added more cell help messages
2016-03-29 15:14:43 +02:00
Clifford Wolf
8c8b2e72b1
Fixed indenting in techlibs/greenpak4/gp_dff.lib
2016-03-29 13:44:14 +02:00
Andrew Zonenberg
75f0030458
Added keep constraint to GP_SYSRESET cell
2016-03-28 23:16:43 -07:00
Andrew Zonenberg
ea9cc03092
Added GP_SYSRESET block
2016-03-28 22:49:46 -07:00
Andrew Zonenberg
3197b6c372
Added GP_COUNT8/GP_COUNT14 cells
2016-03-26 23:29:02 -07:00
Andrew Zonenberg
31a7567aff
Changed GP_LFOSC parameter configuration
2016-03-26 14:13:52 -07:00
Andrew Zonenberg
44fd3cd149
Added GP_LFOSC cell
2016-03-26 13:42:53 -07:00
Andrew Zonenberg
af15b92c86
Renamed GP4_V* cells to GP_V* for consistency
2016-03-26 13:42:41 -07:00
Clifford Wolf
b4bf787f10
Added GP_DFFS, GP_DFFR, and GP_DFFSR
2016-03-23 08:46:10 +01:00
Clifford Wolf
456c10f16e
Added GP_DFF INIT parameter
2016-03-23 08:12:54 +01:00
Clifford Wolf
ca8f8e30f2
Improvements in synth_greenpak4, added -part option
2016-03-21 09:44:52 +01:00
Clifford Wolf
ff5c61b120
Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
Clifford Wolf
a75f94ec4a
Run dffsr2dff in synth_xilinx
2016-02-13 08:20:19 +01:00
Clifford Wolf
0ccfb88728
Work around DDR dout sim glitches in ice40 SB_IO sim model
2016-02-07 11:19:48 +01:00
Clifford Wolf
d69395ca08
Added dffsr2dff
2016-02-02 17:19:01 +01:00
Clifford Wolf
bd10927f45
Progress in cell library documentation
2016-02-01 13:58:10 +01:00
Clifford Wolf
17372d8abd
Added "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 12:40:32 +01:00
Clifford Wolf
2ee608246f
Re-run ice40_opt in "synth_ice40 -abc2"
2015-12-22 12:19:11 +01:00
Clifford Wolf
3102ffbb83
Improvements in ice40_opt
2015-12-22 12:18:38 +01:00
Clifford Wolf
8bf452c364
Bugfix in ice40_ffinit
2015-12-22 12:18:06 +01:00
Clifford Wolf
ec93d258a4
Improved ice40_ffinit
2015-12-22 11:15:25 +01:00
Clifford Wolf
f1b959dc69
Run opt_const before check in default scripts
2015-12-22 11:15:05 +01:00
Clifford Wolf
494e5f24f9
Added "synth_ice40 -abc2"
2015-12-08 11:16:26 +01:00
Clifford Wolf
4d0a6dac7b
Merge pull request #108 from cseed/master
...
Added LO to ICESTORM_LC for LUT cascade route.
2015-12-07 03:32:20 +01:00
Cotton Seed
9f5b6e4cbc
Added LO to ICESTORM_LC for LUT cascade route.
2015-12-06 17:24:48 -05:00
Clifford Wolf
0793f1b196
Added ice40_ffinit pass
2015-11-26 18:11:06 +01:00
Clifford Wolf
8ff229a3ea
Fixed WE/RE usage in iCE40 BRAM mapping
2015-11-24 10:51:34 +01:00
Clifford Wolf
3ad742056b
Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling
2015-11-06 17:02:16 +01:00
Clifford Wolf
864808992b
Bugfix in Xilinx LUT mapping
2015-10-30 13:58:03 +01:00
Clifford Wolf
bbcbf739e6
Progress on cell help messages
2015-10-20 16:49:11 +02:00
Clifford Wolf
5d1c0ce7c0
Progress on cell help messages
2015-10-17 02:35:19 +02:00
Clifford Wolf
25c1f6e605
Added "prep" command
2015-10-14 22:46:41 +02:00
Clifford Wolf
87adb523aa
Added more cell descriptions
2015-10-14 20:30:59 +02:00
Clifford Wolf
7d3a3a3173
Added first help messages for cell types
2015-10-14 16:27:42 +02:00
Clifford Wolf
f42218682d
Added examples/ top-level directory
2015-10-13 15:41:20 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
598a475724
Added nlutmap
2015-09-18 21:57:34 +02:00
Clifford Wolf
745d56149d
Renamed GreenPAK4 cells, improved GP4 DFF mapping
2015-09-18 12:00:37 +02:00
Clifford Wolf
d9cecabb87
Fixed copy&paste typo in synth_greenpak4
2015-09-16 09:39:31 +02:00
Clifford Wolf
c5352f45c3
Added GreenPAK4 skeleton
2015-09-16 09:28:37 +02:00
Clifford Wolf
99ccb3180d
Fixed ice40 handling of negclk RAM40
2015-09-10 17:35:19 +02:00
Clifford Wolf
c475deec6c
Switched to Python 3
2015-08-22 09:59:33 +02:00
Clifford Wolf
9596fe74de
Another bugfix for ice40 and xilinx brams_init make rules
2015-08-16 21:39:34 +02:00
Clifford Wolf
aedcfd6fd3
Fixed Makefile rules for generated share files
2015-08-16 21:15:07 +02:00
Clifford Wolf
d5b1a90b33
Added $tribuf and $_TBUF_ sim models
2015-08-16 13:05:32 +02:00
Clifford Wolf
9c33172ece
Added tribuf command
2015-08-16 12:55:25 +02:00
Clifford Wolf
ff50bc2ac3
Added $tribuf and $_TBUF_ cell types
2015-08-16 12:54:52 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
c43f38c81b
Improved handling of "keep" attributes in hierarchical designs in opt_clean
2015-08-12 14:10:14 +02:00
Marcus Comstedt
c9e56bc428
Added iCE40 WARMBOOT cell
2015-08-06 22:58:17 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
516e8828f2
Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
2015-07-27 22:44:01 +02:00
Clifford Wolf
c6ca4780e2
iCE40 DFF sim models: init Q regs to 0
2015-07-20 13:05:18 +02:00
Clifford Wolf
54588a276a
Avoid tristate warning for blackbox ice40/cells_sim.v
2015-07-18 11:59:04 +02:00
Clifford Wolf
85aaf08e53
Improved liberty file test case
2015-07-06 17:45:56 +02:00
Clifford Wolf
f0c9a099d2
Added "synth -nofsm"
2015-07-02 15:25:38 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
df0163cd2b
iCE40: set min bram efficiency to 2%
2015-06-20 09:31:19 +02:00
Clifford Wolf
ed128b82d7
Added "synth -nordff -noalumacc"
2015-06-15 17:07:40 +02:00
Clifford Wolf
9500b564ac
synth_ice40 now flattens by default
2015-06-09 20:28:17 +02:00
Clifford Wolf
09ef279b60
Added iCE40 PLL cells
2015-05-31 13:10:43 +02:00
Clifford Wolf
c329233f0d
Added output args to synth_ice40
2015-05-26 17:08:53 +02:00
Clifford Wolf
313f570fcc
improved ice40 SB_IO sim model
2015-05-23 10:17:03 +02:00
Clifford Wolf
264eb8eb6e
Added ice40 SB_IO sim model
2015-05-23 09:30:24 +02:00
Clifford Wolf
61512b6f41
Verific build fixes
2015-05-17 08:19:52 +02:00
Clifford Wolf
9d067fecea
ice40_opt bugfix
2015-04-27 11:36:13 +02:00
Clifford Wolf
310fde197e
iCE40: SB_CARRY const fold -> unmap SB_LUT
2015-04-27 10:27:50 +02:00
Clifford Wolf
794d22969d
Added simplemap $lut support
2015-04-27 10:16:07 +02:00
Clifford Wolf
8d4a675f91
Added iCE40 const folding support for SB_CARRY
2015-04-27 08:38:14 +02:00
Clifford Wolf
752851954b
Initialization support for all iCE40 bram modes
2015-04-26 08:39:31 +02:00
Clifford Wolf
b4d7a590e8
initialized iCE40 brams (mode 0)
2015-04-25 20:44:51 +02:00
Clifford Wolf
4cc4400514
improved iCE40 SB_RAM40_4K simulation model
2015-04-25 20:01:37 +02:00
Clifford Wolf
82a4722f46
More iCE40 bram improvements
2015-04-25 18:04:57 +02:00
Clifford Wolf
687f5a5b12
iCE40 bram progress
2015-04-24 15:38:11 +02:00
Clifford Wolf
308a59aa18
iCE40 bram tests and fixes
2015-04-24 08:32:07 +02:00
Clifford Wolf
d6f7698f59
Added ice40 bram support
2015-04-24 00:06:50 +02:00
Clifford Wolf
1277d1bcb8
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
2015-04-19 21:37:40 +02:00
Clifford Wolf
49ef830464
added sync reset to ice40 test_ffs.sh
2015-04-18 09:41:31 +02:00
Clifford Wolf
f564a65851
Added ice40 test_arith
2015-04-18 09:33:34 +02:00
Clifford Wolf
f78fa718be
Added ice40 SB_CARRY support
2015-04-18 09:33:08 +02:00
Clifford Wolf
661b647559
Added mapping of synchronous set/reset to iCE40 flow
2015-04-17 11:54:25 +02:00
Clifford Wolf
31755ed1cf
Changed ice40 ICESTORM_CARRYCONST port name
2015-04-16 12:09:14 +02:00
Clifford Wolf
dc30b034f7
Fixed "dff2dffe -direct-match"
2015-04-16 11:47:59 +02:00
Clifford Wolf
3e9e6e1c22
Added simple ice40 dff tests
2015-04-16 11:31:15 +02:00
Clifford Wolf
0d344a23d3
improved ice40 dff cell mapping
2015-04-16 11:30:56 +02:00
Clifford Wolf
4529c56cc6
use "hierarchy -auto-top" in synth_ice40
2015-04-14 13:45:15 +02:00
Clifford Wolf
06ce496f8d
more cells in ice40 cell library
2015-04-14 13:44:43 +02:00
Clifford Wolf
3481f46d1e
Improved xilinx "bram1" test
2015-04-09 17:12:12 +02:00
Clifford Wolf
7319951145
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
Clifford Wolf
229825e1b8
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 13:37:07 +02:00
Clifford Wolf
b00cad81d7
Towards DRAM support in Xilinx flow
2015-04-09 08:17:14 +02:00
Clifford Wolf
8520b7fbe0
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
Clifford Wolf
d19866615b
Added Xilinx test case for initialized brams
2015-04-06 13:27:11 +02:00
Clifford Wolf
4389d9306e
Added Xilinx bram black-box modules
2015-04-06 08:44:30 +02:00
Clifford Wolf
95944eb69e
make all vector-size related integer params in $mem sim model signed
...
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
2015-04-05 17:26:53 +02:00
Clifford Wolf
706631225e
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-05 09:45:14 +02:00
Clifford Wolf
c52a4cdeed
Added "dffinit", Support for initialized Xilinx DFF
2015-04-04 19:00:15 +02:00
Clifford Wolf
e468d4cc60
Fixes in cmos_cells.v
2015-03-25 09:00:41 +01:00
Clifford Wolf
42d5d94a5d
Added very first version of "synth_ice40"
2015-03-05 20:37:55 +01:00
Clifford Wolf
b005eedf36
Added $assume cell type
2015-02-26 18:04:10 +01:00
Clifford Wolf
4d34d031f9
Added "stat" to "synth" and "synth_xilinx"
2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9
Added final checks to "synth" and "synth_xilinx"
2015-02-15 13:00:00 +01:00
Clifford Wolf
ec05242c27
Smaller default parameters in $mem simlib model
2015-02-15 00:20:05 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f
Added $meminit cell type
2015-02-14 10:23:03 +01:00
Clifford Wolf
04cb947d6a
Added "check" command
2015-02-13 14:34:51 +01:00
Clifford Wolf
d58c3eca3a
Some test related fixes
...
(incl. removal of three bad test cases)
2015-02-12 17:45:44 +01:00
Clifford Wolf
853e949c0e
Disabled (unused) Xilinx tristate buffers
2015-02-04 16:33:59 +01:00
Clifford Wolf
bebbf2e5a4
no support for 6-series xilinx devices
2015-02-01 23:06:44 +01:00
Clifford Wolf
3cbfa3815e
Removed old XST-based xilinx examples
2015-02-01 17:10:46 +01:00
Clifford Wolf
816fe6bbe0
Added Xilinx example for Basys3 board
2015-02-01 17:09:34 +01:00
Clifford Wolf
1b159bc955
Added missing ports and parameters to xilinx brams
2015-02-01 15:42:59 +01:00
Clifford Wolf
1df81f92ce
Added "make mklibyosys", some minor API changes
2015-02-01 13:38:46 +01:00
Clifford Wolf
bedd46338f
Added "fsm -encfile"
2015-01-30 22:46:53 +01:00
Clifford Wolf
909a95182b
Fixed xilinx FDSE sim model
2015-01-24 11:03:22 +01:00
Clifford Wolf
e13a45ae61
Added $equiv cell type
2015-01-19 11:55:05 +01:00
Clifford Wolf
d29d26f882
Various cleanups in xilinx techlib
2015-01-18 19:43:54 +01:00
Clifford Wolf
8d295730e5
Refactoring of memory_bram and xilinx brams
2015-01-18 19:05:29 +01:00
Clifford Wolf
279a18c9a3
Added synth_xilinx -retime -flatten
2015-01-17 20:47:18 +01:00
Clifford Wolf
7031231145
Added MUXCY and XORCY support to synth_xilinx
2015-01-17 15:39:54 +01:00
Clifford Wolf
3ed4e34380
Added cells.lib
2015-01-16 15:50:42 +01:00
Clifford Wolf
dff8bd3b2a
Added dff2dffe to synth_xilinx
2015-01-16 15:49:15 +01:00
Clifford Wolf
7bde74cd2a
Added more FF types to xilinx/cells.v
2015-01-16 15:24:54 +01:00
Clifford Wolf
6b09153320
Fixed xilinx bram clock inverted config
2015-01-16 15:11:56 +01:00
Clifford Wolf
fd8c8d4fd3
Added FF cells to xilinx/cells_sim.v
2015-01-16 14:59:40 +01:00
Clifford Wolf
b197279f3c
Added Xilinx MUXF7 and MUXF8 support
2015-01-15 13:50:04 +01:00
Clifford Wolf
153d3dd4e0
Various cleanups in synth_xilinx command
2015-01-13 13:20:32 +01:00
Clifford Wolf
1d96277f5d
Added add_share_file Makefile macro
2015-01-08 00:23:18 +01:00
Clifford Wolf
38dfc5c580
added minimalistic xilinx sim models
2015-01-08 00:05:11 +01:00
Clifford Wolf
d1e38693d5
More Xilinx bram cleanups
2015-01-07 01:59:36 +01:00
Clifford Wolf
584c5f3937
Cleanups in xilinx bram descriptions
2015-01-07 01:28:18 +01:00
Clifford Wolf
08c13f635c
Xilinx RAMB36/RAMB18 memory_bram support complete
2015-01-06 23:54:33 +01:00
Clifford Wolf
ec2eef89fa
Towards Xilinx bram support
2015-01-06 23:21:52 +01:00
Clifford Wolf
7cc5192125
small fix in xilinx/brams.v
2015-01-06 17:21:18 +01:00
Clifford Wolf
9474928672
Towards Xilinx bram support
2015-01-06 15:26:33 +01:00
Clifford Wolf
4a0b3a5423
Various small improvements to synth_xilinx
2015-01-06 14:37:50 +01:00
Clifford Wolf
081e1a49f8
Towards Xilinx bram support
2015-01-06 14:26:51 +01:00
Clifford Wolf
9c7f47bbd5
Towards Xilinx bram support
2015-01-06 13:33:51 +01:00
Clifford Wolf
9ea2511fe8
Towards Xilinx bram support
2015-01-05 13:59:04 +01:00
Clifford Wolf
8898897f7b
Towards Xilinx bram support
2015-01-04 14:23:30 +01:00
Clifford Wolf
a7e43ae3d9
Progress in memory_bram
2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703
Added proper clkpol support to memory_bram
2015-01-02 22:57:08 +01:00
Clifford Wolf
474831643c
New $mem simlib model
2015-01-02 17:11:31 +01:00
Clifford Wolf
327a5d42b6
Progress in memory_bram
2014-12-31 22:50:08 +01:00
Clifford Wolf
94e6b70736
Added memory_bram (not functional yet)
2014-12-31 16:53:53 +01:00
Clifford Wolf
ba43cf5807
Fixed simlib entries for $memrd and $memwr
2014-12-30 13:33:29 +01:00
Clifford Wolf
c64b1de11d
Fixed build with SMALL=1
2014-12-30 11:41:24 +01:00
Clifford Wolf
4aa9fbbf3f
Improvements in simplemap api, added $ne $nex $eq $eqx support
2014-12-24 10:49:24 +01:00
Clifford Wolf
72f500c950
Removed UTF-8 chars from techmap.v
2014-12-12 12:44:16 +01:00
Clifford Wolf
f1764b4fe9
Added $dffe cell type
2014-12-08 10:50:19 +01:00
Clifford Wolf
fad9cec47b
Added $_DFFE_??_ cell types
2014-12-08 10:43:38 +01:00
Clifford Wolf
74ef92b9c8
Added "abc" label in synth script
2014-10-31 03:46:27 +01:00
Clifford Wolf
ab28491f27
Added "opt -full" alias for all more aggressive optimizations
2014-10-31 03:36:51 +01:00
Clifford Wolf
c3e779a65f
Added $_BUF_ cell type
2014-10-03 10:12:28 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
4888d61c65
Improvements in "synth" script
2014-09-18 12:57:55 +02:00
Clifford Wolf
6644e27cd4
Fixed $macc simlib model for zero-config
2014-09-16 08:19:35 +02:00
Clifford Wolf
7815f81c32
Added "synth" command
2014-09-14 16:09:06 +02:00
Clifford Wolf
923bbbeaf0
Using alumacc in techmap.v
2014-09-14 14:50:15 +02:00
Clifford Wolf
44b5bd4b63
Fixed simlib $macc model for xilinx xsim
2014-09-08 17:09:39 +02:00
Clifford Wolf
fcb46138ce
Simplified $fa undef model
2014-09-08 16:59:39 +02:00
Clifford Wolf
6dc07eb1f2
Fixes and cleanups for blackbox.v
2014-09-08 13:31:04 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
dd887cc025
Using maccmap for $macc and $mul techmap
2014-09-07 18:24:08 +02:00
Clifford Wolf
9329a76818
Various bug fixes (related to $macc model testing)
2014-09-06 20:30:46 +02:00
Clifford Wolf
fa64942018
Added $macc SAT model
2014-09-06 19:44:11 +02:00
Clifford Wolf
bff4706b62
Added $macc simlib model (also use as techmap rule for now)
2014-09-06 17:59:12 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
635b922afe
Undef-related fixes in simlib $alu model
2014-09-02 23:21:59 +02:00
Clifford Wolf
c38283dbd0
Small bug fixes in $not, $neg, and $shiftx models
2014-09-02 17:48:41 +02:00
Clifford Wolf
9923762461
Fixed "test_cell -simlib all"
2014-09-01 15:37:56 +02:00
Clifford Wolf
8649b57b6f
Added $lut support in test_cell, techmap, satgen
2014-08-31 17:43:31 +02:00
Clifford Wolf
4724d94fbc
Added $alu cell type
2014-08-30 18:59:05 +02:00
Clifford Wolf
eb571cba6a
Replaced $__alu CO/CS outputs with full-width CO output
2014-08-30 15:12:39 +02:00
Clifford Wolf
a92a68ce52
Using "via_celltype" in $mul carry-save-acc implementation
2014-08-18 14:30:20 +02:00
Clifford Wolf
6f33fc3e87
Performance fix for new $__lcu techmap rule
2014-08-18 00:27:54 +02:00
Clifford Wolf
4b3834e0cc
Replaced recursive lcu scheme with bk adder
2014-08-18 00:03:33 +02:00
Clifford Wolf
976bda7102
Multiply using a carry-save accumulator
2014-08-16 21:07:29 +02:00
Clifford Wolf
47c2637a96
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
Clifford Wolf
1ddf150c35
Changes in techmap $__alu interface
2014-08-16 16:01:58 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
5602cbde9f
Simplified $__arraymul techmap rule
2014-08-14 20:53:21 +02:00
Clifford Wolf
13f2f36884
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
Clifford Wolf
7e758d5fbb
Added techmap support for actual lookahead carry unit
2014-08-13 18:40:57 +02:00
Clifford Wolf
9a065509ac
Preparations for lookahead ALU support in techmap.v
2014-08-13 16:36:30 +02:00
Clifford Wolf
c27120fcbc
New interface for $__alu in techmap.v
2014-08-13 13:04:28 +02:00
Clifford Wolf
312ee00c9e
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
Clifford Wolf
014a41fcf3
Implemented recursive techmap
2014-08-03 12:40:43 +02:00
Clifford Wolf
1202f7aa4b
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
Clifford Wolf
41555cde10
Reorganized stdcells.v (no actual code change, just moved and indented stuff)
2014-07-31 02:21:06 +02:00
Clifford Wolf
2541489105
Added techmap CONSTMAP feature
2014-07-30 22:04:30 +02:00
Clifford Wolf
6c05badc43
New techmap default rules for $shr $sshr $shl $sshl
2014-07-30 18:49:12 +02:00
Clifford Wolf
2145e57ef0
Bugfix in simlib.v for iverilog
2014-07-29 19:23:31 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
f1ca93a0a3
Fixed simlib.v model for $mem
2014-07-17 16:48:36 +02:00
Clifford Wolf
dcdd5c11b4
Updated simlib to new $mem/$memwr interface
2014-07-16 11:46:40 +02:00
Clifford Wolf
7370ae01e9
Added SIMLIB_NOLUT to simlib.v
2014-04-02 21:28:33 +02:00
Clifford Wolf
e24797add0
Added SIMLIB_NOSR to simlib.v
2014-04-02 21:06:55 +02:00
Clifford Wolf
d4a1b0af5b
Added support for dlatchsr cells
2014-03-31 14:14:40 +02:00
Clifford Wolf
7aa2d746b7
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:42:58 +01:00
Clifford Wolf
973507d85b
Fixes for improved techmap of shifts with large B inputs
2014-03-06 13:33:12 +01:00
Clifford Wolf
8406e7f7b6
Strictly zero-extend unsigned A-inputs of shift operations in techmap
2014-03-06 12:15:44 +01:00
Clifford Wolf
d7f29bb23f
Improved techmap of shift with wide B inputs
2014-03-06 12:14:20 +01:00
Clifford Wolf
fc3b3c4ec3
Added $slice and $concat cell types
2014-02-07 17:44:57 +01:00
Clifford Wolf
a6750b3753
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
Clifford Wolf
ed8ad99960
More changes to techlibs/common/simlib.v for LEC
2014-01-31 11:21:29 +01:00
Clifford Wolf
6a7d7e847d
Added test comments to techlibs/cmos/cmos_cells.lib
2014-01-29 10:51:02 +01:00
Clifford Wolf
a86f33653d
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
2014-01-29 00:36:03 +01:00
Clifford Wolf
1e67099b77
Added $assert cell
2014-01-19 14:03:40 +01:00
Clifford Wolf
3d7a1491aa
Fixed $lut simlib model for a wider range of tools
2014-01-18 19:31:40 +01:00
Clifford Wolf
2fbaaaca7a
More changes to simlib to make it friendlier to a wider range of tools
2014-01-18 19:13:43 +01:00
Clifford Wolf
4a9e133fab
Fixed a type in $mem model in simlib.v
2014-01-18 18:54:50 +01:00
Clifford Wolf
bef17eeb10
Removed cases of trailing comma in stdcells.v
2014-01-18 15:36:17 +01:00
Clifford Wolf
5b96675696
Added $bu0 cell to simlib.v
2014-01-18 15:35:15 +01:00
Clifford Wolf
db9cf544b8
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
Clifford Wolf
b3b00f1bf4
Various small cleanups in stdcells.v techmap code
2013-12-31 15:41:40 +01:00
Clifford Wolf
c69c416d28
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
Clifford Wolf
369bf81a70
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
Clifford Wolf
76f7c10cfc
Using simplemap mappers from techmap
2013-11-24 23:31:14 +01:00
Clifford Wolf
1afe6589df
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Clifford Wolf
20175afd29
Added "techmap -share_map" option
2013-11-24 19:50:25 +01:00
Clifford Wolf
ae798d3fd5
Fixed xilinx/example_sim_counter test bench
2013-11-24 17:55:46 +01:00
Clifford Wolf
532091afcb
Added more generic _TECHMAP_ wire mechanism to techmap pass
2013-11-23 15:58:06 +01:00
Clifford Wolf
1c4a6411af
Updated abc
2013-11-21 22:39:10 +01:00
Clifford Wolf
0c91f890c9
Install simlib in datdir
2013-11-19 23:05:46 +01:00
Clifford Wolf
97f2979bba
Added commented-out osu025 maping commands to cmos techmap example
2013-11-18 12:01:00 +01:00
Clifford Wolf
e5b974fa2a
Cleanups and bugfixes in response to new internal cell checker
2013-11-11 00:39:45 +01:00
Clifford Wolf
404b46674b
Fixed techmap of $reduce_xnor with multi-bit outputs
2013-11-07 00:58:06 +01:00
Clifford Wolf
b41740060b
Fixed techmap of $gt and $ge with multi-bit outputs
2013-11-06 22:59:45 +01:00
Clifford Wolf
6fcbc79b5c
Improved width extension with regard to undef propagation
2013-11-06 21:05:11 +01:00
Clifford Wolf
0b4a64ac6a
Added DFFSR cell to techlibs/cmos/cmos_cells.lib
2013-10-31 12:27:35 +01:00
James Walmsley
40b3551b45
[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
...
Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
2013-10-27 21:48:39 +01:00
Clifford Wolf
88cd2eadf5
Cleanups in xilinx examples
2013-10-27 09:58:53 +01:00
Clifford Wolf
4a3669d871
Added synth_xilinx command
2013-10-27 09:51:06 +01:00
Clifford Wolf
90b016716b
Moved simple xilinx counter sim example to subdir
2013-10-27 09:30:17 +01:00
Clifford Wolf
02f321b6fc
Xilinx mojo_counter example is now working
2013-10-27 08:21:56 +01:00
Clifford Wolf
d635f8adaa
Renamed techlibs/xilinx7 to techlibs/xilinx
2013-10-26 22:29:40 +02:00
Clifford Wolf
4007b41d40
Improved xilinx mojo_counter example
2013-10-26 22:28:42 +02:00
Clifford Wolf
b934a2d209
Added another xilinx example (not funcional yet)
2013-10-26 17:22:29 +02:00
Clifford Wolf
0836a1f2ba
Bugfix in dffsr techmap rules
2013-10-18 13:24:44 +02:00
Clifford Wolf
8197169f8d
Added techmap rules for $sr, $dffsr and $dlatch
2013-10-18 12:29:21 +02:00
Clifford Wolf
e0f693cbb0
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00
Clifford Wolf
5998c101a4
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
Clifford Wolf
5745d3de9a
Added map, par and bitgen to xlinx7 example
2013-10-16 10:57:18 +02:00
Clifford Wolf
288ba9618a
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
Clifford Wolf
2c9bd23801
Added spice testbench to techlibs/cmos
2013-09-14 13:29:11 +02:00
Clifford Wolf
bbe5aa446b
Added spice backend
2013-09-14 11:23:45 +02:00
Clifford Wolf
6685ad436e
Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)
2013-08-27 13:12:26 +02:00
Clifford Wolf
5059b31660
Added simple xilinx7 technology mapping files
2013-08-22 20:31:04 +02:00
Clifford Wolf
a860efa8ac
Implemented same div-by-zero behavior as found in other synthesis tools
2013-08-15 21:00:06 +02:00
Clifford Wolf
c8763301b4
Added $div and $mod technology mapping
2013-08-09 17:09:24 +02:00
Clifford Wolf
ad9bbcbf40
Added $lut cells and abc lut mapping support
2013-07-23 16:19:34 +02:00
Clifford Wolf
7daeee340a
Fixed shift ops with large right hand side
2013-07-09 18:59:59 +02:00
Clifford Wolf
0c6ffc4c65
More fixes for bugs found using xsthammer
2013-06-13 11:18:45 +02:00
Clifford Wolf
7f3f25841e
More sign-extension related fixes
2013-06-10 21:04:04 +02:00
Clifford Wolf
29d6ebd961
Implemented technology mapping for multipliers (using array multiplier)
2013-06-03 12:48:44 +02:00
Clifford Wolf
32dbf7752d
Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
2013-04-07 16:42:29 +02:00
Clifford Wolf
d60fbaf664
Added EXTRA_TARGETS Makefile variable
2013-03-28 16:53:40 +01:00
Clifford Wolf
26f2439551
Tiny bugfix in simlib.v
2013-03-26 19:06:28 +01:00
Clifford Wolf
6960df7285
Fixed stdcells.v for $adff with undef reset value
2013-03-24 10:43:05 +01:00
Clifford Wolf
11789db206
More support code for $sr cells
2013-03-14 11:15:00 +01:00
Clifford Wolf
6543917fb8
added .gitignore files
2013-01-05 11:19:11 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00