Miodrag Milanovic
31b7a9c312
Add expect option to logger command
2020-02-14 12:21:16 +01:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Claire Wolf
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental
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Add log_experimental() and experimental() API and "yosys -x"
2020-01-29 15:25:03 +01:00
Eddie Hung
6d27d43727
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
Claire Wolf
5c2508cef8
Improve logging use of experimental features
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-28 17:51:50 +01:00
Claire Wolf
cef607c8b7
Add log_experimental() and experimental() API and "yosys -x"
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 18:27:47 +01:00
Claire Wolf
de6006fbc8
Merge pull request #1613 from porglezomp-misc/version-flag-alias
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Add --version and -version as aliases for -V
2020-01-27 12:59:27 +01:00
Eddie Hung
ade57058f7
As before, only display MEM if Linux or FreeBSD
2020-01-14 11:38:48 -08:00
Eddie Hung
a901a5fb44
print_stats footer to return peak memory, option for including children
2020-01-14 11:25:23 -08:00
Eddie Hung
67c9c41f7e
Move abc9.* constpad entries to Abc9Pass::on_register()
2020-01-09 17:10:54 -08:00
Eddie Hung
dd718838bb
Merge remote-tracking branch 'origin/clifford/onpassreg' into eddie/abc9_scratchpad
2020-01-09 17:06:13 -08:00
Clifford Wolf
cd92a974f4
Add Pass::on_register() and Pass::on_shutdown()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-09 21:36:34 +01:00
Eddie Hung
fbd9636e08
Add abc9.if.script.flow{,2} to constpad
2020-01-08 12:15:01 -08:00
Eddie Hung
a63e2508fc
Add RTLIL::constpad, init by yosys_setup(); use for abc9
2020-01-08 10:52:08 -08:00
Cassie Jones
b76b023584
Add --version and -version as aliases for -V
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The flag --version is commonly accepted by command line tools.
The code for the version flags added here matches the pattern used for
the help flag aliases, for consistency.
Fixes #1612
2020-01-05 03:19:02 -05:00
Clifford Wolf
3edb2e708b
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-02 18:58:45 +01:00
whitequark
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
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Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
Eddie Hung
6bf7114bbd
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
2019-10-04 16:45:36 -07:00
Eddie Hung
279fd22ddf
Add Const::{begin,end,empty}()
2019-10-04 15:00:57 -07:00
Eddie Hung
62c66406ad
log_dump() to support State enum
2019-10-02 17:49:07 -07:00
Eddie Hung
d963e8c2c6
Fix typo
2019-09-30 15:18:40 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Eddie Hung
d5f0794a53
Merge pull request #1414 from hzeller/improve-replace-with-empty-map
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Avoid work in replace() if rules empty.
2019-09-29 19:35:23 -07:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Henner Zeller
8c2b4f0a50
Avoid work in replace() if rules empty.
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This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382 .
Signed-off-by: Henner Zeller <h.zeller@acm.org>
2019-09-29 00:17:40 -07:00
Miodrag Milanovic
d0493925ec
Support binary files for backends, fixes #1407
2019-09-28 09:36:18 +02:00
Miodrag Milanovic
435300f930
Make read/write gzip files on macos works, fixes #1357
2019-09-26 19:35:12 +02:00
Eddie Hung
9a84e4711c
Spacing
2019-09-13 16:30:44 -07:00
Eddie Hung
5473e597bf
Use template specialisation
2019-09-13 11:13:57 -07:00
Eddie Hung
95e80809a5
Revert "SigSet<Cell*> to use stable compare class"
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This reverts commit 4ea34aaacd
.
2019-09-13 09:49:15 -07:00
Eddie Hung
c487a8ff25
Grammar
2019-09-12 12:00:34 -07:00
Eddie Hung
c05a403dd1
static_assert to enforce this going forward
2019-09-12 11:45:17 -07:00
Eddie Hung
4ea34aaacd
SigSet<Cell*> to use stable compare class
2019-09-12 11:45:02 -07:00
Clifford Wolf
e9f3eb9760
Bump year in copyright notice
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:43:16 +02:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
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Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
Eddie Hung
3b19c3657c
Move namespace alias
2019-08-16 19:37:11 +00:00
Eddie Hung
0b9ee4fbbf
Try this for gcc-4.8?
2019-08-15 16:20:54 -07:00
Eddie Hung
453a9429b6
Fix spacing
2019-08-15 14:54:41 -07:00
Eddie Hung
52355f5185
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
Clifford Wolf
49301b733e
Merge branch 'master' into clifford/fix1255
2019-08-15 22:44:38 +02:00
Eddie Hung
4cfefae21e
More use of IdString::in()
2019-08-15 09:23:57 -07:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Clifford Wolf
b25cf36856
Add YOSYS_NO_IDS_REFCNT configuration macro
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 12:23:16 +02:00
Clifford Wolf
390bf459fb
Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
Clifford Wolf
8222c5735e
More improvements and cleanups in IdString subsystem
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- better use of "inline" keyword
- deprecate "sticky" IDs feature
- improve handling of empty ID
- add move constructor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
Clifford Wolf
b5534b66c8
Improve API of ID() macro
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
71eff6f0de
RTLIL::S{0,1} -> State::S{0,1} for headers
2019-08-07 11:14:03 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Clifford Wolf
9260e97aa2
Automatically prune init attributes in verific front-end, fixes #1237
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 15:31:49 +02:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
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wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
Clifford Wolf
c5d56fbe2d
Merge pull request #1253 from YosysHQ/clifford/check
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Be less aggressive with running design->check()
2019-08-07 12:14:41 +02:00
Clifford Wolf
338f6765eb
Tweak default gate costs, cleanup "stat -tech cmos"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 10:25:51 +02:00
Eddie Hung
234fcf1724
Fix typos
2019-08-06 19:07:45 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
e38f40af5b
Use IdString::begins_with()
2019-08-06 16:42:25 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
Clifford Wolf
100c377451
Redesign of cell cost API
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 01:12:14 +02:00
Eddie Hung
84f52aee0d
Add SigSpec::extract_end() convenience function
2019-08-06 15:25:11 -07:00
Eddie Hung
0b56be8c56
Restore original SigSpec::extract()
2019-08-06 15:24:55 -07:00
Eddie Hung
26cb3e7afc
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
2019-08-06 14:50:00 -07:00
Clifford Wolf
95a6582f34
Be less aggressive with running design->check()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 19:21:37 +02:00
David Shah
27360ceda6
Add support for writing gzip-compressed files
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 17:43:04 +01:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Miodrag Milanovic
f767179c75
New mxe hacks needed to support 2ca237e
2019-08-01 17:28:07 +02:00
Miodrag Milanovic
3e4307c104
Fix case when file does not exist
2019-07-29 12:29:13 +02:00
David Shah
6538671c84
Merge pull request #1226 from YosysHQ/dave/gzip
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Add support for gzip'd input files
2019-07-27 07:40:38 +01:00
David Shah
da6701c4cd
Fix frontend auto-detection for gzipped input
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:29:05 +01:00
David Shah
933db0410e
Add support for reading gzip'd input files
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:23:58 +01:00
Jakob Wenzel
70882a8070
replaced std::iterator with using statements
2019-07-25 09:51:09 +02:00
Jakob Wenzel
25685a9a5b
made ObjectIterator extend std::iterator
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this makes it possible to use std algorithms on them
2019-07-24 16:35:40 +02:00
Eddie Hung
54708dfbd7
Add an SigSpec::at(offset, defval) convenience method
2019-07-19 13:54:57 -07:00
Eddie Hung
25ff27e37f
SigSpec::extract to take negative lengths
2019-07-19 12:34:04 -07:00
Eddie Hung
06f94c92d4
Revert "Add log_checkpoint function and use it in opt_muxtree"
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This reverts commit 0e6c83027f
.
2019-07-15 08:35:48 -07:00
Clifford Wolf
44fd459c79
Redesign log_id_cache so that it doesn't keep IdString instances referenced, fixes #1178
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-15 17:10:42 +02:00
Clifford Wolf
0e6c83027f
Add log_checkpoint function and use it in opt_muxtree
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-15 12:12:21 +02:00
Clifford Wolf
ef07a313b4
Merge pull request #1162 from whitequark/rtlil-case-attrs
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Allow attributes on individual switch cases in RTLIL
2019-07-09 16:56:29 +02:00
Eddie Hung
41d7d9d24b
Clarify script -scriptwire doc
2019-07-08 19:21:21 -07:00
whitequark
93bc5affd3
Allow attributes on individual switch cases in RTLIL.
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The parser changes are slightly awkward. Consider the following IL:
process $0
<point 1>
switch \foo
<point 2>
case 1'1
assign \bar \baz
<point 3>
...
case
end
end
Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.
To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.
Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
Eddie Hung
f1504696e5
Use Pass::call_on_module() as per @cliffordwolf comments
2019-07-02 08:20:37 -07:00
Eddie Hung
02ba85b133
script -select -> script -scriptwire
2019-07-02 08:17:26 -07:00
Eddie Hung
06971385fa
Support ability for "script -select" to take commands from wires
2019-06-28 13:36:33 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig
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"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Eddie Hung
fb30fcb7c5
Undo iterator based Module::remove() for cells, as containers will not
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invalidate
2019-06-27 15:03:21 -07:00
Bogdan Vukobratovic
0f32cb4e0a
Merge remote-tracking branch 'upstream/master'
2019-06-27 12:11:47 +02:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Ben Widawsky
8767ec3fbd
Add a few more filename rewrites
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This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"
Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-20 10:27:59 -07:00
Clifford Wolf
73bd1d59a7
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
2019-06-20 13:04:04 +02:00
Clifford Wolf
b3441935b1
Merge pull request #1100 from bwidawsk/home
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Support ~ in filename parsing
2019-06-19 10:52:59 +02:00
whitequark
df6576edc8
In RTLIL::Module::check(), check process invariants.
2019-06-19 05:22:13 +00:00
Ben Widawsky
468c41d997
Support ~ for home directory
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This is tested on Linux only
v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-18 14:38:40 -07:00
Eddie Hung
b45d06d7a3
Fix leak removing cells during ABC integration; also preserve attr
2019-06-17 12:54:24 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Bogdan Vukobratovic
8451cbea89
Move netlist helper module to passes/opt for the time being
2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic
fe651922cb
Merge remote-tracking branch 'upstream/master'
2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic
53695e6729
Prepare for situation when port of the signal cannot be found
2019-06-14 11:39:24 +02:00