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Commit Graph

6700 Commits

Author SHA1 Message Date
Sergey 27134be135
Merge pull request #1 from YosysHQ/Sergey/tests_ice40 
tests_ice40 improvements
 2019-08-23 06:50:19 +03:00
Eddie Hung fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung 36cf0a3dd5 Remove adffs_tb.v 2019-08-22 16:50:14 -07:00
Eddie Hung 51ffb093b5 In sat: 'x' in init attr should not override constant 2019-08-22 16:43:08 -07:00
Eddie Hung c50d68653d Spelling 2019-08-22 16:06:36 -07:00
Eddie Hung 698a0e3aaf WIP for equivalency checking memories 2019-08-22 16:05:12 -07:00
Eddie Hung 43e7c4917a Do not print OKAY 2019-08-22 16:05:12 -07:00
Eddie Hung 65e6c23abd Spelling 2019-08-22 16:05:12 -07:00
Eddie Hung 5061d239ae Fail if iverilog fails 2019-08-22 16:05:12 -07:00
Eddie Hung 8e3754bdb4 Hide tri-state warning message for now 2019-08-22 16:05:12 -07:00
Eddie Hung 659a481482 Remove unused output 2019-08-22 16:05:12 -07:00
Eddie Hung 61087329ef Fix tribuf test 2019-08-22 16:05:12 -07:00
Eddie Hung f9906eed68 Fix comments 2019-08-22 16:05:12 -07:00
Eddie Hung 9224b3bc17 Remove tech independent synthesis 2019-08-22 16:05:12 -07:00
Eddie Hung 388eb3288c Remove dffe instantation 2019-08-22 16:04:50 -07:00
Eddie Hung 9e537a76b5 Move $dffe to dffs.{v,ys} 2019-08-22 16:04:48 -07:00
Eddie Hung c5754d9e8b Make multiplier wider, do not do tech independent synth 2019-08-22 16:04:07 -07:00
Miodrag Milanovic 7fafaa896d do not require boost if pyosys is not used 2019-08-22 11:57:46 -07:00
Chris Shucksmith 68e673d687 require tcl-tk in Brewfile 2019-08-22 11:57:25 -07:00
Eddie Hung 2fe35f902b
Merge pull request #1322 from mmicko/pyosys_osx 
do not require boost if pyosys is not used
 2019-08-22 11:53:27 -07:00
Miodrag Milanovic e5dac8096d do not require boost if pyosys is not used 2019-08-22 20:43:52 +02:00
Eddie Hung 926cd10350
Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk 
require tcl-tk in Brewfile
 2019-08-22 11:32:44 -07:00
Eddie Hung b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx 
opt_expr to trim A port of $shiftx/$shift
 2019-08-22 10:31:27 -07:00
Clifford Wolf 5e0f6c9ae5 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:54 +02:00
Clifford Wolf e9f3eb9760 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:16 +02:00
Clifford Wolf 151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:09:37 +02:00
Clifford Wolf 2c8c8b3c74
Merge pull request #1289 from mmicko/anlogic_fixes 
Anlogic fixes and optimization
 2019-08-22 18:09:10 +02:00
Clifford Wolf 4c449caf9b Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:06:36 +02:00
Clifford Wolf 4d37710e82
Merge pull request #1281 from mmicko/efinix 
Initial support for Efinix Trion series FPGAs
 2019-08-22 18:06:02 +02:00
Eddie Hung 9245f0d3f5 Copy-paste typo 2019-08-22 08:43:44 -07:00
Chris Shucksmith d0322e9584 require tcl-tk in Brewfile 2019-08-22 16:37:40 +01:00
Eddie Hung 6f971470f8 Respect opt_expr -keepdc as per @cliffordwolf 2019-08-22 08:37:27 -07:00
Eddie Hung 379f33af54 Handle $shift and Y_WIDTH > 1 as per @cliffordwolf 2019-08-22 08:22:23 -07:00
Eddie Hung 9e31f01b34 Add cover() 2019-08-22 08:06:24 -07:00
Eddie Hung d0ffe7544c Canonical form 2019-08-22 08:05:01 -07:00
Clifford Wolf 34a7c0209d
Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg 
mem2reg to preserve user attributes and src
 2019-08-22 10:24:42 +02:00
Eddie Hung bb1a8a0190 Add test 2019-08-21 21:58:20 -07:00
Eddie Hung d3a212ff91 opt_expr to trim A port of $shiftx if Y_WIDTH == 1 2019-08-21 21:53:55 -07:00
whitequark 841903582f
Merge pull request #1315 from mmicko/fix_dependencies 
Fix test_pmgen deps
 2019-08-21 21:40:31 +00:00
Eddie Hung a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
SergeyDegtyar d945b8a357 Fix all comments from PR 2019-08-21 21:52:07 +03:00
Miodrag Milanovic 948b6f91a1 Fix test_pmgen deps 2019-08-21 17:00:24 +02:00
Clifford Wolf 7d8db1c053
Merge pull request #1314 from YosysHQ/eddie/fix_techmap 
techmap -max_iter to apply to each module individually
 2019-08-21 09:12:56 +02:00
SergeyDegtyar b835ec37cb Add temp directory 2019-08-21 07:53:34 +03:00
Eddie Hung 076af2e617 Missing newline 2019-08-20 20:37:52 -07:00
Eddie Hung 9b9d759451 Fix copy-paste typo 2019-08-20 20:18:51 -07:00
Eddie Hung fe61dcce8b Grammar 2019-08-20 20:05:51 -07:00
Eddie Hung fce8dc7db2 Add test 2019-08-20 20:05:16 -07:00
Eddie Hung 193eae0c84 techmap -max_iter to apply to each module individually 2019-08-20 19:50:20 -07:00
Eddie Hung 33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00