Clifford Wolf
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7d98645fe8
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Added "make -j{N}" support to "make test"
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2014-07-30 19:23:26 +02:00 |
Clifford Wolf
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e6df25bf74
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Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
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2014-07-29 21:12:50 +02:00 |
Clifford Wolf
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1241a9fd50
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Added "opt_const -fine" and "opt_reduce -fine"
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2014-07-21 16:34:16 +02:00 |
Clifford Wolf
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ec3a798194
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Also simulate unmapped memories in "make test"
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2014-07-17 16:53:52 +02:00 |
Clifford Wolf
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964a67ac41
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Added note to "make test": use git checkout of iverilog
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2014-07-16 10:03:07 +02:00 |
Clifford Wolf
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a67cd2d4a2
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Progress in Verific bindings
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2014-03-17 01:56:00 +01:00 |
Clifford Wolf
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0ac915a757
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Progress in Verific bindings
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2014-03-14 11:46:13 +01:00 |
Clifford Wolf
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772330608a
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Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)
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2014-02-19 12:40:49 +01:00 |
Clifford Wolf
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30379ea20d
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Added frontend (-f) option to autotest.sh
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2014-02-15 15:40:17 +01:00 |
Clifford Wolf
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7664f5d92b
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Updated ABC and some related changes
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2014-02-13 08:07:08 +01:00 |
Clifford Wolf
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9ce7b0fc3b
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Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)
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2014-02-12 13:11:58 +01:00 |
Clifford Wolf
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aa9da46807
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Removed old unused files from tests/
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2014-02-05 01:55:39 +01:00 |
Clifford Wolf
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de9226a64f
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Replaced isim with xsim in tests/tools/autotest.sh, removed xst support
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2014-02-03 13:00:55 +01:00 |
Clifford Wolf
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6dec0e0b3e
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Added autotest.sh -p option
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2014-01-02 17:52:48 +01:00 |
Clifford Wolf
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ab3f6266ad
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Use "abc -dff" in "make test"
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2013-12-31 21:25:34 +01:00 |
Clifford Wolf
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a582b9d184
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Fixed commented out techmap call in tests/tools/autotest.sh
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2013-12-31 13:51:25 +01:00 |
Clifford Wolf
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1afe6589df
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Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
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2013-11-24 20:44:00 +01:00 |
Clifford Wolf
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1e6836933d
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Added modelsim support to autotest
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2013-11-24 15:10:43 +01:00 |
Clifford Wolf
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288ba9618a
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Moved common techlib files to techlibs/common
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2013-09-15 11:52:57 +02:00 |
Clifford Wolf
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c8763301b4
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Added $div and $mod technology mapping
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2013-08-09 17:09:24 +02:00 |
Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
Clifford Wolf
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ff4a1dd06c
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Improved vcdcd.pl (added -d option)
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2013-05-14 09:41:47 +02:00 |
Clifford Wolf
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be8ecd6d16
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Some improvements in vcdcd.pl
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2013-05-14 08:50:59 +02:00 |
Clifford Wolf
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2d9cbd3b02
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added more .gitignore files (make test)
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2013-01-05 11:35:52 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |