Peter Crozier
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
Peter Crozier
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
Peter Crozier
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
whitequark
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
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Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Xiretza
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
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C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
Eddie Hung
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
Claire Wolf
88185f8959
Fix handling of signed indices in bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Alberto Gonzalez
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
Vamsi K Vytla
5f9cd2e2f6
Preserve 'signed'-ness of a verilog wire through RTLIL
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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987 , now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
Marcelina Kościelnicka
06a344efcb
ilang, ast: Store parameter order and default value information.
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Fixes #1819 , #1820 .
2020-04-21 19:09:00 +02:00
Claire Wolf
e1fb12a4b9
Add LookaheadRewriter for proper bitselwrite support
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
Claire Wolf
9b4dab397e
Fix 5bba9c3
, closes #1876
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-14 21:05:07 +02:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Eddie Hung
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Eddie Hung
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
Alberto Gonzalez
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
Eddie Hung
7cfdf4ffa7
verilog: fix $specify3 check
2020-02-13 12:42:04 -08:00
Jeff Wang
16ea4ea61a
partial rebase of PeterCrozier's enum work onto current master
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I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.
Original commit:
"Initial implementation of enum, typedef, import. Still a WIP."
881833aa73
2020-01-16 13:51:47 -05:00
David Shah
f6b5e47e40
sv: Switch parser to glr, prep for typedef
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
whitequark
b1f400aeb8
genrtlil: emit \src attribute on CaseRule.
2019-07-08 12:29:08 +00:00
Clifford Wolf
ec4565009a
Add "read_verilog -pwires" feature, closes #1106
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 14:38:50 +02:00
Clifford Wolf
211d85cfcc
Fixes and cleanups in AST_TECALL handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 12:41:09 +02:00
Clifford Wolf
a3bbc5365b
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
2019-06-07 12:08:42 +02:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor
2019-05-27 19:07:46 +02:00
Stefan Biereigel
ed625a3102
move wand/wor resolution into hierarchy pass
2019-05-27 18:00:22 +02:00
Clifford Wolf
92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range
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Give error instead of asserting for invalid range, fixes #947
2019-05-27 13:26:12 +02:00
Miodrag Milanovic
84ffb21708
Give error instead of asserting for invalid range, fixes #947
2019-05-27 12:25:18 +02:00
Miodrag Milanovic
34417ce55f
Added support for unsized constants, fixes #1022
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Includes work from @sumit0190 and @AaronKel
2019-05-27 11:42:10 +02:00
Stefan Biereigel
85de9d26c1
fix assignment of non-wires
2019-05-23 17:55:56 +02:00
Stefan Biereigel
fd003e0e97
fix indentation across files
2019-05-23 13:57:27 +02:00
Stefan Biereigel
075a48d3fa
implementation for assignments working
2019-05-23 13:57:27 +02:00
Clifford Wolf
87426f5a06
Improve write_verilog specify support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
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(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Clifford Wolf
3b6a02d3a7
Fix width detection of memory access with bit slice, fixes #974
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:57:26 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
b232e027bf
Checking and fixing specify cells in genRTLIL
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
17caaa3fa8
Improve handling of "full_case" attributes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 17:51:21 +01:00
Clifford Wolf
22ff60850e
Add support for SVA labels in read_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 11:17:32 -08:00
Clifford Wolf
3a51714451
Fix error for wire decl in always block, fixes #763
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 11:56:44 -08:00
Clifford Wolf
23148ffae1
Fixes related to handling of autowires and upto-ranges, fixes #814
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
Clifford Wolf
28fba903c5
Fix segfault in printing of some internal error messages
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:40:52 +01:00
Clifford Wolf
807b3c7697
Fix sign handling of real constants
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-13 12:36:47 +01:00
Clifford Wolf
64e0582c29
Various indenting fixes in AST front-end (mostly space vs tab issues)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
Clifford Wolf
23b69ca32b
Improve read_verilog range out of bounds warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-20 23:48:53 +02:00
Ruben Undheim
436e3c0a7c
Refactor code to avoid code duplication + added comments
2018-10-20 16:06:48 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Tom Verbeure
cb214fc01d
Fix for issue 594.
2018-10-02 07:44:23 +00:00
Henner Zeller
68b5d0c3b1
Convert more log_error() to log_file_error() where possible.
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Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
2018-07-20 09:37:44 -07:00
Henner Zeller
b5ea598ef6
Use log_file_warning(), log_file_error() functions.
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Wherever we can report a source-level location.
2018-07-20 08:19:06 -07:00
Henner Zeller
1a60126a34
Provide source-location logging.
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o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
2018-07-19 10:22:02 -07:00
Clifford Wolf
fe2ee833e1
Fix handling of signed memories
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-28 16:57:03 +02:00
Clifford Wolf
4372cf690d
Add (* gclk *) attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 13:25:42 +02:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
8364f509e3
Fix error handling for nested always/initial
2017-12-02 18:52:05 +01:00
Clifford Wolf
8f8baccfde
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
2017-06-07 12:30:24 +02:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
56e2bb88ae
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
aaa99c35bd
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
Clifford Wolf
ab18e9df7c
Added assertpmux
2016-09-07 00:28:01 +02:00
Clifford Wolf
aa25a4cec6
Added $anyconst support to yosys-smtbmc
2016-08-30 19:27:42 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
82a4a0230f
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
Clifford Wolf
f6629b9c29
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
Clifford Wolf
e9fe57c75e
Only allow posedge/negedge with 1 bit wide signals
2016-08-10 19:32:11 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Ruben Undheim
178ff3e7f6
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00
Clifford Wolf
766032c5f8
Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
2016-05-27 17:55:03 +02:00
Clifford Wolf
e9ceec26ff
fixed typos in error messages
2016-05-27 16:37:36 +02:00
Clifford Wolf
5a09fa4553
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Rick Altherr
34969d4140
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()
2016-01-31 09:20:16 -08:00
Clifford Wolf
34f2b84fb6
Fixed handling of parameters and localparams in functions
2015-11-11 10:54:35 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
422794c584
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
2015-03-01 11:20:22 +01:00
Clifford Wolf
1f1deda888
Added non-std verilog assume() statement
2015-02-26 18:47:39 +01:00
Clifford Wolf
c2ba4fb2fd
Convert floating point cell parameters to strings
2015-02-18 23:35:23 +01:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
a8e9d37c14
Creating $meminit cells in verilog front-end
2015-02-14 10:49:30 +01:00
Clifford Wolf
234a45a3d5
Ignore explicit assignments to constants in HDL code
2015-02-08 00:58:03 +01:00
Clifford Wolf
c8305e3a6d
Fixed a bug with autowire bit size
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(removed leftover from when we tried to auto-size the wires)
2015-02-08 00:48:23 +01:00