Eddie Hung
c29f0c5048
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
2019-02-28 09:31:24 -08:00
Clifford Wolf
63be3f3bab
Improvements in "supercover" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:45:13 -08:00
Clifford Wolf
a58dbcf2ba
Add "supercover" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-27 11:37:08 -08:00
Larry Doolittle
7a40294e93
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
Jim Lawson
171c425cf9
Fix FIRRTL to Verilog process instance subfield assignment.
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Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
2019-02-25 16:18:13 -08:00
David Shah
fa2f595cfa
ecp5: Compatibility with Migen AsyncResetSynchronizer
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-25 13:24:30 +00:00
Clifford Wolf
c258b99040
Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:41:36 +01:00
Clifford Wolf
c118f9a377
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
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Define basic_cell_type() function and use it to derive the cell type …
2019-02-24 11:39:13 -08:00
Clifford Wolf
cd722f26a5
Cleanups in ARST handling in wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:34:23 +01:00
Clifford Wolf
da14bc8524
Merge pull request #824 from litghost/fix_reduce_on_ff
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Fix WREDUCE on FF not fixing ARST_VALUE parameter.
2019-02-24 11:29:14 -08:00
Clifford Wolf
1816fe06af
Fix handling of defparam for when default_nettype is none
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
Clifford Wolf
a516b4fb5a
Check if Verific was built with DB_PRESERVE_INITIAL_VALUE
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 19:51:30 +01:00
Jim Lawson
71bcc4c644
Address requested changes - don't require non-$ name.
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Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
2019-02-22 16:06:10 -08:00
Keith Rothman
25680f6a07
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
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Adds test case that fails without code change.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-22 10:30:42 -08:00
Clifford Wolf
c521f4632f
Merge pull request #819 from YosysHQ/clifford/optd
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Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
2019-02-22 06:55:48 +01:00
Clifford Wolf
25a3a96107
Merge pull request #820 from YosysHQ/clifford/fix810
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Fix #810 and fix #814
2019-02-22 06:54:48 +01:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress
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Improve ABC netname preservation
2019-02-22 01:16:34 +01:00
Clifford Wolf
362ef36ccd
Fix Travis
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It looks like that whole "Fixing Travis's git clone" code was just
there to make the "git describe --tags" work. I simply removed both.
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-22 00:15:55 +01:00
Clifford Wolf
d55790909c
Hotfix for 4c82ddf
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 19:27:23 +01:00
Clifford Wolf
3b97b612fe
Merge pull request #822 from litghost/expand_setundef
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Add -params mode to force undef parameters in selected cells.
2019-02-21 19:24:16 +01:00
Keith Rothman
4c82ddf394
Add -params mode to force undef parameters in selected cells.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-21 10:16:38 -08:00
Clifford Wolf
0e371109b0
Merge pull request #818 from YosysHQ/clifford/dffsrfix
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Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
2019-02-21 18:58:44 +01:00
Clifford Wolf
03aa3541ae
Merge pull request #786 from YosysHQ/pmgen
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Pattern Matcher Generator and iCE40 DSP Mapper
2019-02-21 18:56:01 +01:00
Clifford Wolf
893194689d
Fix typo in passes/pmgen/README.md
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:50:02 +01:00
Clifford Wolf
310b0a0ffa
Merge pull request #821 from eddiehung/dff_init
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Revert "Add -B option to autotest.sh to append to backend_opts"
2019-02-21 18:46:58 +01:00
Clifford Wolf
23148ffae1
Fixes related to handling of autowires and upto-ranges, fixes #814
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
Eddie Hung
8e789da74c
Revert "Add -B option to autotest.sh to append to backend_opts"
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This reverts commit 281f2aadca
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2019-02-21 09:22:29 -08:00
Clifford Wolf
974927adcf
Fix handling of expression width in $past, fixes #810
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:55:33 +01:00
Clifford Wolf
28fba903c5
Fix segfault in printing of some internal error messages
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:40:52 +01:00
Clifford Wolf
0a6588569b
Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 15:51:59 +01:00
Clifford Wolf
953e0bf88d
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 14:27:46 +01:00
Clifford Wolf
2da4c9c8f0
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:49:45 +01:00
Clifford Wolf
2fe1c830eb
Bugfix in ice40_dsp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 13:28:46 +01:00
Eddie Hung
31fea5eb33
Merge pull request #817 from eddiehung/dff_init
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Cleanup #805
2019-02-20 17:26:56 -08:00
Eddie Hung
4035ec8933
Remove simple_defparam tests
2019-02-20 15:45:45 -08:00
Clifford Wolf
84999a7e68
Add ice40 test_dsp_map test case generator
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb
Add "synth_ice40 -dsp"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:42:27 +01:00
Clifford Wolf
246391200e
Add FF support to wreduce
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 16:36:42 +01:00
Clifford Wolf
7bf4e4a185
Improve iCE40 SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 12:55:20 +01:00
Clifford Wolf
dca65d83a0
Detect and reject cases that do not map well to iCE40 DSPs (yet)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-20 11:18:19 +01:00
Eddie Hung
d365682a21
Add aiger tests to make tests
2019-02-19 15:25:47 -08:00
Jim Lawson
5c4a72c43e
Fix normal (non-array) hierarchy -auto-top.
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Add simple test.
2019-02-19 14:35:15 -08:00
Eddie Hung
78873d5bbb
Merge branch 'master' into read_aiger
2019-02-19 12:33:22 -08:00
Eddie Hung
2a8e5bf953
Merge pull request #805 from eddiehung/dff_init
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write_verilog to write initial statement for initial flop state
2019-02-19 12:32:40 -08:00
David Shah
bb56cb738d
ecp5: Add DDRDLLA
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 19:34:37 +00:00
Eddie Hung
843e7fc8a7
Fix for using POSIX basename
2019-02-19 09:02:37 -08:00
David Shah
c36f15b489
ecp5: Add DELAYF/DELAYG blackboxes
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Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-19 14:10:43 +00:00
Clifford Wolf
62493c91b2
Add first draft of functional SB_MAC16 model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-19 14:47:27 +01:00
Eddie Hung
8e1dbfac3a
Missing OSX headers?
2019-02-17 20:59:53 -08:00