whitequark
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
...
support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
whitequark
0e1beb6f30
Merge pull request #1880 from jjj11x/duplicate_enum
...
duplicated enum item names should result in an error
2020-04-14 12:39:28 +00:00
whitequark
5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser
...
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 08:40:45 +00:00
Alberto Gonzalez
8a84674a42
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 04:22:00 +00:00
David Shah
0a178de1b3
verilog: Fix write to deleted object
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-12 18:49:09 +01:00
whitequark
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow
...
Improve handling of integer literals in RTLIL frontend
2020-04-09 04:02:57 +00:00
Henner Zeller
c15040c218
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
Jeff Wang
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
Jeff Wang
249876b614
support using previously declared types/localparams/params in package
...
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
whitequark
b494d4c656
read_ilang: improve style. NFC.
...
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-06 18:31:15 +00:00
whitequark
d22888ce74
read_ilang: improve error message for overly long wires.
...
Fixes #1838 .
2020-04-06 10:33:02 +00:00
whitequark
ca70a1049f
read_ilang: detect overflow of integer literals.
2020-04-06 10:32:02 +00:00
Eddie Hung
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
...
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-02 12:27:10 -07:00
Eddie Hung
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
...
IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
Eddie Hung
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
Claire Wolf
c69f4b246a
Merge pull request #1846 from dh73/ast_fe
...
Adding error message for when size (width) of number literal is zero
2020-04-02 18:15:15 +02:00
Eddie Hung
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
Eddie Hung
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
...
kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
David Shah
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc
...
verilog: Add location info for generate constructs
2020-04-01 20:55:24 +01:00
David Shah
c3997c77a5
verilog: Add location info for generate constructs
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-01 18:47:20 +01:00
Eddie Hung
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
Claire Wolf
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
...
ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
Eddie Hung
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
Diego H
c859bcf71b
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
Diego H
92809bb1d3
Adding error message for when size (width) of number literal is zero
2020-03-30 17:18:13 -06:00
Eddie Hung
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
...
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
Alberto Gonzalez
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
...
Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
N. Engelhardt
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines
...
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
Claire Wolf
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
...
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
Peter Crozier
f8c065ed1c
Inline productions to follow house style.
2020-03-27 16:21:45 +00:00
Rupert Swarbrick
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
...
This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Alberto Gonzalez
6040593994
Revert over-aggressive change to a more modest cleanup.
2020-03-27 09:46:40 +00:00
Peter Crozier
9a8a644ad1
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
Peter Crozier
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
Peter Crozier
6cad865d12
Simplify was not being called for packages. Broke typedef enums.
2020-03-22 18:20:46 -07:00
Peter Crozier
c06eda2504
Build pkg_user_types before parsing in case of changes in the design.
2020-03-22 18:20:46 -07:00
Peter
0aaa36ca6d
Clear pkg_user_types if no packages following a 'design -reset-vlog'.
2020-03-22 18:20:46 -07:00
Peter
14f32028ec
Parser changes to support typedef.
2020-03-22 18:20:46 -07:00
Eddie Hung
f828cb5132
Merge pull request #1788 from YosysHQ/eddie/fix_ndebug
...
Fix NDEBUG warnings
2020-03-19 14:58:06 -07:00
Miodrag Milanović
d46259becd
Merge pull request #1787 from YosysHQ/mmicko/lexer_deps
...
Add dependency to verilog_lexer.cc
2020-03-19 18:24:40 +01:00
Miodrag Milanovic
dc75ed7dac
Add one mode dependency
2020-03-19 16:53:40 +01:00
Eddie Hung
43092f063f
Fix NDEBUG warnings
2020-03-19 08:48:39 -07:00
N. Engelhardt
b473264a06
Merge pull request #1775 from huaixv/asserts_locations
...
Add precise locations for asserts
2020-03-19 13:12:18 +01:00
Alberto Gonzalez
eb30d66d01
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-19 07:29:00 +00:00
huaixv
cd82ccd258
Add precise locations for asserts
2020-03-19 10:22:07 +08:00
Eddie Hung
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
Alberto Gonzalez
6dd2024965
Add AST node source location information in a couple more parser rules.
2020-03-17 06:22:12 +00:00
Miodrag Milanović
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
...
refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
Miodrag Milanović
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations
...
Set AST node source location in more parser rules.
2020-03-14 11:18:39 +02:00
Marcus Comstedt
5e94bf0291
refixed parsing of constant with comment between size and value
...
The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
2020-03-11 18:21:44 +01:00
jiegec
7b679eecb3
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
Eddie Hung
2d63bf5877
verilog: also set location for simple_behavioral_stmt
2020-03-10 10:29:24 -07:00
Alberto Gonzalez
da8270aa01
Set AST source locations in more parser rules.
2020-03-10 01:50:39 +00:00
Claire Wolf
a7cc4673c3
Fix partsel expr bit width handling and add test case
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
Claire Wolf
d59da5a4e4
Fix bison warning for "pure-parser" option
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-03 08:41:55 -08:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
...
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
Claire Wolf
91892465e1
Merge pull request #1681 from YosysHQ/eddie/fix1663
...
verilog: instead of modifying localparam size, extend init constant expr
2020-03-03 08:34:31 -08:00
Eddie Hung
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
...
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
Eddie Hung
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
Eddie Hung
825b96fdcf
Comment out log()
2020-02-27 16:53:49 -08:00
Eddie Hung
e79376d6cb
ast: quiet down when deriving blackbox modules
2020-02-27 10:17:29 -08:00
Alberto Gonzalez
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
...
Improve specify parser
2020-02-21 09:15:17 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
...
Enum support
2020-02-20 18:17:25 +01:00
Eddie Hung
ea4bd161b6
verilog: add support for more delays than just rise/fall
2020-02-19 11:09:37 -08:00
Jeff Wang
a31ba8e5d5
remove unnecessary blank line
2020-02-17 04:42:49 -05:00
Jeff Wang
d12ba42a74
add attributes for enumerated values in ilang
...
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
Jeff Wang
6320f2692b
separate out enum_item/param implementation when they should be different
2020-02-17 04:42:30 -05:00
Eddie Hung
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
Eddie Hung
6b58c1820c
verilog: improve specify support when not in -specify mode
2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Eddie Hung
7cfdf4ffa7
verilog: fix $specify3 check
2020-02-13 12:42:04 -08:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing
...
Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
whitequark
c34d7b13f4
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
...
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-02-07 00:41:54 +00:00
Rodrigo Alejandro Melo
da485dc007
Modified $readmem[hb] to use '\' or '/' according the OS
...
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:10:29 -03:00
Eddie Hung
fc33287bc1
verilog: instead of modifying localparam size, extend init constant expr
2020-02-05 17:19:42 -08:00
Stefan Biereigel
b844b078db
correct wire declaration grammar for #1614
2020-02-03 21:29:40 +01:00
Rodrigo Alejandro Melo
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
...
Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
Rodrigo Alejandro Melo
71f3afb9a2
Replaced strlen by GetSize into simplify.cc
...
As recommended in CodingReadme.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:44:09 -03:00
David Shah
4bfd2ef4f3
sv: Improve handling of wildcard port connections
...
Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
5df591c023
hierarchy: Resolve SV wildcard port connections
...
Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
50f86c11b2
sv: Add lexing and parsing of .* (wildcard port conns)
...
Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf
...
ast: Add support for $sformatf system function
2020-02-02 14:53:46 +00:00
Rodrigo Alejandro Melo
b4c30cfc8d
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided
...
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:03:56 -03:00
Rodrigo Alejandro Melo
d74b9604e3
Modified the new search for files of $readmem[hb] to be backward compatible
...
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 22:10:51 -03:00
Rodrigo Alejandro Melo
7b3fe404ab
$readmem[hb] file inclusion is now relative to the Verilog file
...
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 18:20:22 -03:00
Claire Wolf
2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand
...
Add Verific support for OPER_REDUCE_NAND
2020-01-30 19:55:53 +01:00
Claire Wolf
60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help
...
`verific` pass to print help message when command syntax error
2020-01-30 18:05:16 +01:00
Claire Wolf
ffadaddab5
Merge pull request #1654 from YosysHQ/eddie/sby_fix69
...
verific: unflatten struct ports
2020-01-30 18:03:35 +01:00
Claire Wolf
23c44afaed
Add Verific support for OPER_REDUCE_NAND
...
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-30 18:01:13 +01:00
Eddie Hung
6d27d43727
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
Eddie Hung
ce6a690d27
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
...
Now done in read_aiger
2020-01-27 13:30:27 -08:00
Eddie Hung
f443695a38
Merge remote-tracking branch 'origin/master' into eddie/verific_help
2020-01-27 10:34:10 -08:00
Eddie Hung
d730bba6d2
verific: no help() when no YOSYS_ENABLE_VERIFIC
2020-01-27 10:32:18 -08:00
Eddie Hung
7b445121cc
verific: also unflatten for 'hierarchy' flow as per @cliffordwolf
2020-01-27 10:15:22 -08:00
Eddie Hung
c7fbe13db5
read_aiger: set abc9_box_seq attr
2020-01-24 13:11:43 -08:00
Eddie Hung
cccc0ae112
verific: unflatten struct ports
2020-01-24 10:12:52 -08:00
Eddie Hung
73526a6f10
read_aiger: also parse abc9_mergeability
2020-01-22 14:21:25 -08:00
Eddie Hung
cd093c00f8
read_aiger: discard LUT inputs with nodeID == 0; not < 2
2020-01-21 11:56:30 -08:00
Eddie Hung
7f728bc116
read_aiger: ignore constant inputs on LUTs
2020-01-21 11:16:50 -08:00
David Shah
22c967e35e
ast: Add support for $sformatf system function
...
Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
Jeff Wang
98c6bd7630
fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6
...
The if(str == node->str) is in fact necessary (otherwise causes generate
for in Multiplier_2D in tests/simple/multiplier.v to fail with error
message "Right hand side of 3rd expression of generate for-loop is not
constant!"). Note: in PeterCrozier's implementation, the break only
breaks out of the switch-case, not the outer for loop.
2020-01-17 02:07:42 -05:00
Jeff Wang
549deb6373
fix enum in generate blocks
2020-01-16 18:13:30 -05:00
Jeff Wang
41a0a93dcc
allow enums to be declared at toplevel scope
2020-01-16 18:13:14 -05:00
Jeff Wang
cc2236d0c0
lexer doesn't seem to return TOK_REG for logic anymore
2020-01-16 18:08:58 -05:00
Jeff Wang
5ddf84d430
allow enum typedefs
2020-01-16 17:17:42 -05:00
Jeff Wang
16ea4ea61a
partial rebase of PeterCrozier's enum work onto current master
...
I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.
Original commit:
"Initial implementation of enum, typedef, import. Still a WIP."
881833aa73
2020-01-16 13:51:47 -05:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
05c8858a90
read_aiger: $lut prefix in front
2020-01-15 14:31:32 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Eddie Hung
f63f76c372
read_aiger: also rename "$0"
2020-01-14 09:01:53 -08:00
Eddie Hung
2c65e1abac
abc9: break SCC by setting (* keep *) on output wires
2020-01-13 21:45:27 -08:00
Eddie Hung
ee95fa959a
read_aiger: uniquify wires with $aiger<autoidx> prefix
2020-01-13 21:28:27 -08:00
Eddie Hung
766e16b525
read_aiger: make $and/$not/$lut the prefix not suffix
2020-01-13 17:34:37 -08:00
Eddie Hung
d979648b7a
read_aiger: more accurate debug message
2020-01-09 10:02:19 -08:00
Eddie Hung
943ea4bf9e
read_aiger: do not double-count outputs for flops
2020-01-09 08:55:36 -08:00
Eddie Hung
2ca8c10e7a
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-07 15:43:22 -08:00
Eddie Hung
2ac36031d4
read_aiger: consistency between ascii and binary; also name latches
2020-01-07 13:30:31 -08:00
Eddie Hung
8f5388ea5b
read_aiger fixes
2020-01-07 11:59:57 -08:00
Eddie Hung
b94cf0c126
read_aiger: connect identical signals together
2020-01-07 11:43:28 -08:00
Eddie Hung
baba33fbd3
read_aiger: cope with latches and POs with same name
2020-01-07 11:22:48 -08:00
Eddie Hung
738af17a26
read_aiger: default -clk_name to be empty
2020-01-07 11:21:45 -08:00
Eddie Hung
61a2a60595
read_aiger: do not process box connections, work standalone
2020-01-07 09:48:11 -08:00
Eddie Hung
b57f692a9e
read_aiger: consistency between ascii and binary
2020-01-07 09:32:34 -08:00
Eddie Hung
83616e7866
read_aiger: add -xaiger option
2020-01-06 12:43:29 -08:00
Eddie Hung
96db05aaef
parse_xaiger to not take box_lookup
2019-12-31 17:06:03 -08:00
Eddie Hung
e5ed8e8e21
parse_xaiger to reorder ports too
2019-12-31 16:50:22 -08:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531
...
verilog: preserve size of $genval$-s in for loops
2019-12-19 12:21:33 -05:00
Clifford Wolf
22dd9f107c
Send people to symbioticeda.com instead of verific.com
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-18 13:06:34 +01:00
Eddie Hung
a6fdb9f5c1
aiger frontend to user shorter, $-prefixed, names
2019-12-17 15:50:01 -08:00
Eddie Hung
5f50e4f112
Cleanup xaiger, remove unnecessary complexity with inout
2019-12-17 15:45:26 -08:00
Eddie Hung
0875a07871
read_xaiger to cope with optional '\n' after 'c'
2019-12-17 15:45:26 -08:00
Eddie Hung
c0339bbbf1
Name inputs/outputs of aiger 'i%d' and 'o%d'
2019-12-13 16:21:09 -08:00
Rodrigo Alejandro Melo
e9dc2759c4
Fixed some missing "verilog_" in documentation
2019-12-13 10:17:05 -03:00
Eddie Hung
1ac1697e15
Stray log_dump
2019-12-11 16:59:00 -08:00
Eddie Hung
af36943cb9
Preserve size of $genval$-s in for loops
2019-12-11 16:52:37 -08:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
ab667d3d47
Call abc9 with "&write -n", and parse_xaiger() to cope
2019-12-06 16:35:57 -08:00
Eddie Hung
69d8c1386a
Do not connect undriven POs to 1'bx
2019-12-06 16:21:06 -08:00
Clifford Wolf
7dece7955e
Merge pull request #1551 from whitequark/manual-cell-operands
...
Clarify semantics of comb cells, in particular shifts
2019-12-05 08:24:24 -08:00
whitequark
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
...
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
Marcin Kościelnicki
0ce22cea46
read_ilang: do bounds checking on bit indices
2019-11-27 22:24:39 +01:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Clifford Wolf
db323685a4
Add Verific support for SVA nexttime properties
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 16:11:56 +01:00
Clifford Wolf
e93e4a7a2c
Improve handling of verific primitives in "verific -import -V" mode
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 16:00:07 +01:00
Clifford Wolf
6af0d03fae
Add Verific SVA support for "always" properties
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 15:52:21 +01:00
David Shah
9e4801cca7
sv: Correct parsing of always_comb, always_ff and always_latch
...
Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:27:19 +00:00
Eddie Hung
a576747483
Consistent log message, ignore 's' extension
2019-11-20 15:40:46 -08:00
Clifford Wolf
55bda2b2c6
Correctly treat empty modules as blackboxes in Verific
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:56:31 +01:00
Clifford Wolf
f6ff311a1d
Do not rename VHDL entities to "entity(impl)" when they are top modules
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:54:10 +01:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Eddie Hung
e2819ce31c
Oops
2019-11-19 13:25:38 -08:00
Eddie Hung
84711f0e8c
Print help message for verific pass
2019-11-19 13:24:48 -08:00
Clifford Wolf
65f197e28f
Add check for valid macro names in macro definitions
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-07 13:30:03 +01:00
Clifford Wolf
84982b3083
Improve naming scheme for (VHDL) modules imported from Verific
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 12:13:50 +02:00
Clifford Wolf
d49c6b2cba
Add "verific -L"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 09:14:03 +02:00
Clifford Wolf
5025aab8c9
Add "verilog_defines -list" and "verilog_defines -reset"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 13:35:56 +02:00
Clifford Wolf
4033ff8c2e
Fix handling of "restrict" in Verific front-end
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 12:39:28 +02:00
Clifford Wolf
71936209cf
Fix parsing of .cname BLIF statements
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 09:06:57 +02:00
Clifford Wolf
935d3e19e2
Add .blackbox support to blif front-end
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 00:00:27 +02:00
Clifford Wolf
e84cedfae4
Use "(id)" instead of "id" for types as temporary hack
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-14 05:24:31 +02:00
Eddie Hung
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
...
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Miodrag Milanovic
c0b14cfea7
Fixes for MSVC build
2019-10-04 16:29:46 +02:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Clifford Wolf
468b8a5178
Merge pull request #1419 from YosysHQ/eddie/lazy_derive
...
module->derive() to be lazy and not touch ast if already derived
2019-10-03 12:06:12 +02:00
David Shah
e46e8753c8
frontends/ast: code style
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:55:43 +01:00
David Shah
5501d9090a
sv: Fix typedefs in blocks
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
David Shah
8cc1bee33c
sv: Disambiguate interface ports
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
David Shah
c0bb47beca
sv: Fix memories of typedefs
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
497faf4ec0
sv: Add %expect
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
af25585170
sv: Add support for memories of a typedef
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
30d2326030
sv: Add support for memory typedefs
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
e70e4afb60
sv: Fix typedefs in packages
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
c962951612
sv: Fix typedef parameters
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40
sv: Switch parser to glr, prep for typedef
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
Miodrag Milanovic
c026579c20
Define environ, fixes #1424
2019-10-01 18:45:07 +02:00
Eddie Hung
f9bb335294
Cleanup $currQ from aigerparse
2019-09-30 16:36:42 -07:00
Eddie Hung
0a1af434e8
Fix for svinterfaces
2019-09-30 14:52:04 -07:00
Eddie Hung
08b55a20e3
module->derive() to be lazy and not touch ast if already derived
2019-09-30 14:11:01 -07:00
Eddie Hung
8684b58bed
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 12:29:35 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc
...
rpc: new frontend
2019-09-30 17:38:20 +00:00
whitequark
99a7f39084
rpc: new frontend.
...
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.
Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
2019-09-30 15:53:11 +00:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
...
Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Miodrag Milanovic
9e55b234b4
Fix reading aig files on windows
2019-09-29 15:40:37 +02:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Eddie Hung
c340fbfab2
Force $inout.out ports to begin with '$' to indicate internal
2019-09-23 21:58:04 -07:00
Clifford Wolf
8da0888bf6
Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 12:16:20 +02:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
...
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
Clifford Wolf
25b08b1afd
Fix handling of range selects on loop variables, fixes #1372
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-16 11:25:37 +02:00
Clifford Wolf
a67d63714b
Fix handling of z_digit "?" and fix optimization of cmp with "z"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-13 13:39:39 +02:00
Clifford Wolf
855e6a9b91
Fix lexing of integer literals without radix
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-13 10:19:58 +02:00
Clifford Wolf
7eb593829f
Fix lexing of integer literals, fixes #1364
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-12 09:43:32 +02:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival
...
Allow arrival times of sequential outputs to be specified to abc9
2019-09-05 12:00:23 -07:00
Clifford Wolf
4b7202c9c2
Merge pull request #1350 from YosysHQ/clifford/fixsby59
...
Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
2019-09-05 18:14:28 +02:00
Eddie Hung
ba629e6a28
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-09-04 15:36:07 -07:00
Eddie Hung
d3eea82bc2
Revert "parse_xaiger() to do "clean -purge""
...
This reverts commit 5d16bf8316
.
2019-09-04 15:21:39 -07:00
Eddie Hung
d6a84a78a7
Merge remote-tracking branch 'origin/master' into eddie/deferred_top
2019-09-03 10:49:21 -07:00
Clifford Wolf
25e5fbac90
Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
...
Fixes https://github.com/YosysHQ/SymbiYosys/issues/59
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-02 22:56:38 +02:00
Eddie Hung
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
Eddie Hung
5d16bf8316
parse_xaiger() to do "clean -purge"
2019-08-29 17:24:25 -07:00
Eddie Hung
83ffec26cb
Remove newline
2019-08-29 09:08:58 -07:00
Eddie Hung
6510297712
Restore non-deferred code, deferred case to ignore non constant attr
2019-08-29 09:02:10 -07:00
Eddie Hung
34ae29295d
read_verilog -defer should still populate module attributes
2019-08-28 19:59:09 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
fe1b2337fd
Do not propagate mem2reg attribute through to result
2019-08-22 16:57:59 -07:00
Eddie Hung
a6776ee35e
mem2reg to preserve user attributes and src
2019-08-21 13:36:01 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
...
This reverts commit 091bf4a18b
.
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
be9e4f1b67
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Clifford Wolf
c25c1e742b
Merge pull request #1308 from jakobwenzel/real_params
...
Handle real values when deriving ast modules
2019-08-20 11:37:26 +02:00
Eddie Hung
3f4886e7a3
Fix typo
2019-08-19 10:42:00 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
9bfe924e17
Set abc_flop and use it in toposort
2019-08-19 09:40:01 -07:00
Jakob Wenzel
24971fda87
handle real values when deriving ast modules
2019-08-19 14:17:36 +02:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
...
Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
Clifford Wolf
27d59dc055
Fix erroneous ifndef-NDEBUG in verific.cc
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 14:49:55 +02:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
6b156beda1
Remove unused variable
2019-08-16 13:35:39 -07:00
Eddie Hung
847c54088e
Change signature of parse_blif to take IdString
2019-08-15 10:26:24 -07:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
...
This reverts commit c851dc1310
, reversing
changes made to f54bf1631f
.
2019-08-12 12:06:45 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
...
Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
4f81213165
Merge pull request #1261 from YosysHQ/clifford/verific_init
...
Automatically prune init attributes in verific front-end
2019-08-10 09:47:25 +02:00
Eddie Hung
446dcb3ed3
Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
2019-08-09 09:17:35 -07:00
Eddie Hung
9776084eda
Allow whitebox modules to be overwritten
2019-08-07 16:40:24 -07:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Eddie Hung
03ec8d6551
Run "clean" on mapped_mod in its own design
2019-08-07 09:54:27 -07:00
Clifford Wolf
9260e97aa2
Automatically prune init attributes in verific front-end, fixes #1237
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 15:31:49 +02:00
Clifford Wolf
679bc6507f
Merge pull request #1252 from YosysHQ/clifford/fix1231
...
Fix handling of functions/tasks without top-level begin-end block
2019-08-07 12:14:54 +02:00
David Shah
dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix
...
Improved JSON attr/param encoding
2019-08-07 10:40:38 +01:00
Eddie Hung
ee7c970367
IdString::str().substr() -> IdString::substr()
2019-08-06 19:08:33 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
a6bc9265fb
RTLIL::S{0,1} -> State::S{0,1}
2019-08-06 16:23:37 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Clifford Wolf
f1f5b4e375
Fix handling of functions/tasks without top-level begin-end block, fixes #1231
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 18:06:14 +02:00
Clifford Wolf
f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix
...
Fix formatting for msys2 mingw build
2019-08-02 16:37:57 +02:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Clifford Wolf
292f03355a
Update JSON front-end to process new attr/param encoding
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-01 12:48:22 +02:00
Clifford Wolf
acd8bc0a74
Merge pull request #1233 from YosysHQ/clifford/defer
...
Call "read_verilog" with -defer from "read"
2019-07-31 13:30:52 +02:00
Clifford Wolf
fc462c8243
Call "read_verilog" with -defer from "read"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-29 10:29:36 +02:00
David Shah
92694ea3a9
verilog_lexer: Increase YY_BUF_SIZE to 65536
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 13:35:39 +01:00
Jakob Wenzel
e2fe8e0a4f
initialize noblackbox and nowb in AstModule::clone
2019-07-22 10:37:40 +02:00
Miodrag Milanovic
6cce679b35
Fix typo, double "of"
2019-07-16 11:03:30 +02:00
William D. Jones
da5d64d71e
Fix missing semicolon in Windows-specific code in aigerparse.cc.
...
Signed-off-by: William D. Jones <thor0505@comcast.net>
2019-07-14 13:52:27 -04:00
Eddie Hung
a314565ad4
Short out async box
2019-07-11 10:52:45 -07:00
Eddie Hung
bd198aa803
Missing debug message
2019-07-11 10:07:14 -07:00
Eddie Hung
f8f0ffe786
Small opt
2019-07-10 18:56:50 -07:00
Eddie Hung
4a995c5d80
Change how to specify flops to ABC again
2019-07-10 17:54:56 -07:00
Eddie Hung
a092c48f03
Use split_tokens()
2019-07-10 17:34:51 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
whitequark
b1f400aeb8
genrtlil: emit \src attribute on CaseRule.
2019-07-08 12:29:08 +00:00
whitequark
93bc5affd3
Allow attributes on individual switch cases in RTLIL.
...
The parser changes are slightly awkward. Consider the following IL:
process $0
<point 1>
switch \foo
<point 2>
case 1'1
assign \bar \baz
<point 3>
...
case
end
end
Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.
To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.
Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
Clifford Wolf
e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144
...
Improve specify dummy parser
2019-07-03 12:30:37 +02:00
Clifford Wolf
ba36567908
Some cleanups in "ignore specify parser"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:22:10 +02:00
Eddie Hung
35fd9b0473
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-02 12:35:45 -07:00
Clifford Wolf
d206eca03b
Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-02 11:36:26 +02:00
Eddie Hung
a31e17182d
Refactor and cope with new abc_flop format
2019-07-01 11:50:34 -07:00
Eddie Hung
ac5f3d500d
Fix spacing
2019-07-01 11:10:44 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Eddie Hung
b3f162e94e
Replace log_assert() with meaningful log_error()
2019-06-28 12:54:44 -07:00
Clifford Wolf
af74409749
Improve specify dummy parser, fixes #1144
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-28 10:21:16 +02:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
469f98b6bd
Remove unneeded include
2019-06-27 11:20:40 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Clifford Wolf
f6053b8810
Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 11:09:43 +02:00
Eddie Hung
cec2292b0b
Merge remote-tracking branch 'origin/master' into xaig
2019-06-24 20:01:43 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
f2ead4334a
Reduce log_debug spam in parse_xaiger()
2019-06-21 17:33:49 -07:00
Eddie Hung
b75863ca3f
Workaround issues exposed by gcc-4.8
2019-06-21 14:31:09 -07:00
Miodrag Milanovic
50e7221077
Add upto and offset to JSON ports
2019-06-21 19:47:25 +02:00
Miodrag Milanovic
3775763f51
Fix typo
2019-06-21 19:09:34 +02:00
Clifford Wolf
f15def325c
Added JSON upto and offset
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 15:22:17 +02:00
Clifford Wolf
78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118
...
Make genvar a signed type
2019-06-21 10:13:13 +02:00
Eddie Hung
9faeba7a66
Fix broken abc9.v test due to inout being 1'bx
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
014606affe
Fix issue with part of PI being 1'bx
2019-06-20 17:38:16 -07:00
Eddie Hung
c27ab609fa
Make genvar a signed type
2019-06-20 16:04:12 -07:00
Eddie Hung
20119ee50e
Maintain "is_unsized" state of constants
2019-06-20 12:43:39 -07:00
Clifford Wolf
2428fb7dc2
Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays
2019-06-20 12:03:00 +02:00
Clifford Wolf
ec4565009a
Add "read_verilog -pwires" feature, closes #1106
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 14:38:50 +02:00
Tobias Wölfel
8b8af10f5e
Unpacked array declaration using size
...
Allows fixed-sized array dimension specified by a single number.
This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560 .
But is split out of the original work.
2019-06-19 12:47:48 +02:00
Clifford Wolf
8d0cd529c9
Add defaultvalue attribute
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:37:11 +02:00
Clifford Wolf
6d64e242ba
Fix handling of "logic" variables with initial value
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:25:11 +02:00
Eddie Hung
0c59bc0b75
Cleanup
2019-06-16 10:42:00 -07:00
Eddie Hung
fb90d8c18c
Cleanup
2019-06-16 09:34:26 -07:00
Eddie Hung
3d1185b835
Read init from outputs
2019-06-15 22:41:42 -07:00
Eddie Hung
c04921c3a8
Fix debug message
2019-06-15 18:13:44 -07:00
Eddie Hung
b706ae82de
Fix log_debug messages
2019-06-15 12:42:18 -07:00
Eddie Hung
7a3c403ba0
Missing close bracket
2019-06-15 09:10:01 -07:00
Eddie Hung
2ef2aa997c
read_aiger to not require clk_name for latches, plus debug
2019-06-15 09:07:53 -07:00
Eddie Hung
7876b5b8be
Cover __APPLE__ too for little to big endian
2019-06-14 12:40:51 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Eddie Hung
97d2656375
Resolve comments from @daveshah1
2019-06-14 12:00:02 -07:00
Eddie Hung
a3be25ab0d
Cleanup
2019-06-14 10:27:30 -07:00
Eddie Hung
d005568f2e
Add TODO to parse_xaiger
2019-06-14 10:11:13 -07:00
Eddie Hung
bc22e2e3ee
Optimise some more
2019-06-13 17:02:58 -07:00
Eddie Hung
d09d4e0706
Move ConstEvalAig to aigerparse.cc
2019-06-13 16:28:11 -07:00
Eddie Hung
d39a5a77a9
Add ConstEvalAig specialised for AIGs
2019-06-13 13:13:48 -07:00
Eddie Hung
342fc0a600
parse_xaiger to cope with inouts
2019-06-12 15:45:46 -07:00
Eddie Hung
b21d29598a
Consistency
2019-06-12 09:40:51 -07:00
Eddie Hung
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
Udi Finkelstein
4b56f6646d
Fixed brojen $error()/$info/$warning() on non-generate blocks
...
(within always/initial blocks)
2019-06-11 02:52:06 +03:00
Eddie Hung
2b350401c4
Fix spacing from spaces to tabs
2019-06-07 15:44:57 -07:00
Eddie Hung
6934f4bdd5
Fix spacing (entire file is wrong anyway, will fix later)
2019-06-07 11:30:36 -07:00
Eddie Hung
d00ae1d6a8
Remove unnecessary std::getline() for ASCII
2019-06-07 11:28:25 -07:00
Eddie Hung
a04521c6b7
Fix read_aiger -- create zero driver, fix init width, parse 'b'
2019-06-07 11:07:15 -07:00
Clifford Wolf
211d85cfcc
Fixes and cleanups in AST_TECALL handling
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 12:41:09 +02:00
Clifford Wolf
a3bbc5365b
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
2019-06-07 12:08:42 +02:00
Clifford Wolf
a0b57f2a6f
Cleanup tux3-implicit_named_connection
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection
2019-06-07 11:41:54 +02:00
tux3
88f5977093
SystemVerilog support for implicit named port connections
...
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
2019-06-06 18:07:49 +02:00
Clifford Wolf
b894187cf6
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
...
Added support for parsing attributes on port connections.
2019-06-06 12:34:05 +02:00
Maciej Kurc
03e0d3a17c
Fixed memory leak.
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-05 10:42:43 +02:00
Clifford Wolf
36120fcc30
Only support Symbiotic EDA flavored Verific
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-02 10:14:50 +02:00
Maciej Kurc
a6cadf6318
Added support for parsing attributes on port connections.
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-31 14:58:43 +02:00
Clifford Wolf
2faa1d0e80
Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-30 10:04:26 +02:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor
2019-05-27 19:07:46 +02:00
Stefan Biereigel
cd12f2ddcf
remove leftovers from ast data structures
2019-05-27 18:01:44 +02:00
Stefan Biereigel
ed625a3102
move wand/wor resolution into hierarchy pass
2019-05-27 18:00:22 +02:00
Clifford Wolf
92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range
...
Give error instead of asserting for invalid range, fixes #947
2019-05-27 13:26:12 +02:00
Miodrag Milanovic
84ffb21708
Give error instead of asserting for invalid range, fixes #947
2019-05-27 12:25:18 +02:00
Miodrag Milanovic
34417ce55f
Added support for unsized constants, fixes #1022
...
Includes work from @sumit0190 and @AaronKel
2019-05-27 11:42:10 +02:00
Stefan Biereigel
85de9d26c1
fix assignment of non-wires
2019-05-23 17:55:56 +02:00
Stefan Biereigel
fd003e0e97
fix indentation across files
2019-05-23 13:57:27 +02:00
Stefan Biereigel
075a48d3fa
implementation for assignments working
2019-05-23 13:57:27 +02:00
Stefan Biereigel
9df04d7e75
make lexer/parser aware of wand/wor net types
2019-05-23 13:57:27 +02:00
Eddie Hung
7057753427
Rename label
2019-05-21 18:20:31 -07:00
Eddie Hung
b5a29460b9
Try again
2019-05-21 17:20:19 -07:00
Eddie Hung
1bff09f2ff
Fix warning
2019-05-21 16:26:20 -07:00
Kaj Tuomi
48ddbe52fb
Read bigger Verilog files.
...
Hit parser limit with 3M gate design. This commit fix it.
2019-05-18 14:20:30 +03:00
Clifford Wolf
b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes
...
Support for attributes on parameters and localparams for Verilog frontend
2019-05-16 14:21:18 +02:00
Maciej Kurc
ce4a0954bc
Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:44:16 +02:00
Henner Zeller
8eb2798776
Make the generated *.tab.hh include all the headers needed to define the union.
2019-05-14 21:07:26 -07:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
...
Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf
1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
...
Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf
7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
...
Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
Clifford Wolf
20268d12a5
Fix the other bison warning in ilang_parser.y
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 15:38:43 +02:00
Clifford Wolf
1cd1b5fc1a
Add "real" keyword to ilang format
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:00:40 +02:00
Clifford Wolf
c7f2e93024
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
2019-05-06 11:46:10 +02:00
Ben Widawsky
a98069d762
verilog_parser: Fix Bison warning
...
As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
%name-prefix "frontend_verilog_yy"
For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html
Compile tested only.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-05 19:36:27 -07:00
Clifford Wolf
70d0f389ad
Merge pull request #988 from YosysHQ/clifford/fix987
...
Add approximate support for SV "var" keyword
2019-05-04 21:58:25 +02:00
Clifford Wolf
66d6ca2de2
Add support for SVA "final" keyword
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 09:25:32 +02:00
Clifford Wolf
87426f5a06
Improve write_verilog specify support
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
Clifford Wolf
9804c86e87
Add approximate support for SV "var" keyword, fixes #987
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 07:52:51 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Eddie Hung
c7d7d8ad1b
For hier_tree::Elaborate() also include SV root modules (bind)
2019-05-03 20:53:25 +02:00
Eddie Hung
3ea54ec400
Fix verific_parameters construction, use attribute to mark top netlists
2019-05-03 20:53:25 +02:00
Eddie Hung
a27b42e975
WIP -chparam support for hierarchy when verific
2019-05-03 20:53:25 +02:00
Eddie Hung
0f1a4cc03c
verific_import() changes to avoid ElaborateAll()
2019-05-03 20:53:25 +02:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
...
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Clifford Wolf
6bbe2fdbf3
Add splitcmplxassign test case and silence splitcmplxassign warning
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
Clifford Wolf
3b6a02d3a7
Fix width detection of memory access with bit slice, fixes #974
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:57:26 +02:00
Clifford Wolf
59d74a3348
Re-enable "final loop assignment" feature
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:02:39 +02:00
Clifford Wolf
e35fe1344d
Disabled "final loop assignment" feature
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 20:22:50 +02:00
Clifford Wolf
9c7d23446d
Merge pull request #972 from YosysHQ/clifford/fix968
...
Add final loop variable assignment when unrolling for-loops
2019-04-30 18:09:44 +02:00
Clifford Wolf
84f3a796e1
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:37:46 +02:00
Clifford Wolf
9af825e31e
Add final loop variable assignment when unrolling for-loops, fixes #968
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Eddie Hung
d9c915042a
Move clean from aigerparse to abc9
2019-04-23 13:42:35 -07:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
012c6af088
Allow $specify[23] cells in blackbox modules
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
b232e027bf
Checking and fixing specify cells in genRTLIL
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
41b843c27b
Un-break default specify parser
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be
Add specify parser
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Eddie Hung
5f30a8795d
Tidy up
2019-04-22 17:47:05 -07:00
Eddie Hung
8f30019b68
Revert "Temporarily remove 'r' extension"
...
This reverts commit eaf3c24772
.
2019-04-22 17:41:21 -07:00
Eddie Hung
eaf3c24772
Temporarily remove 'r' extension
2019-04-22 11:54:19 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
bc98a463a4
Merge pull request #952 from YosysHQ/clifford/fix370
...
Determine correct signedness and expression width in for-loop unrolling
2019-04-22 20:10:46 +02:00
Clifford Wolf
4ad0ea5c3c
Determine correct signedness and expression width in for loop unrolling, fixes #370
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
Clifford Wolf
e158ea2097
Add log_debug() framework
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
Clifford Wolf
b40af877f3
Merge pull request #909 from zachjs/master
...
support repeat loops with constant repeat counts outside of constant functions
2019-04-22 08:51:34 +02:00
Eddie Hung
42a6e0b0b9
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
2019-04-21 14:49:18 -07:00
Clifford Wolf
5b7fea5245
Add "noblackbox" attribute
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-21 11:40:09 +02:00
Clifford Wolf
fb7f02be55
New behavior for front-end handling of whiteboxes
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 22:24:50 +02:00
Eddie Hung
21701cc1df
read_aiger to parse 'r' extension
2019-04-18 17:39:36 -07:00
Eddie Hung
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Eddie Hung
e1b550d203
Ignore a/i/o/h XAIGER extensions
2019-04-17 10:55:23 -07:00
Eddie Hung
fecafb2207
Forgot backslashes
2019-04-12 18:22:44 -07:00
Eddie Hung
9bfcd80063
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
2019-04-12 18:21:16 -07:00
Eddie Hung
c776db3320
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-04-12 17:09:24 -07:00
Eddie Hung
acf3f5694b
Fix inout handling for -map option
2019-04-12 17:02:24 -07:00
Eddie Hung
ada130b459
Also cope with duplicated CIs
2019-04-12 16:17:12 -07:00
Eddie Hung
1c6f0cffd9
Cope with an output having same name as an input (i.e. CO)
2019-04-12 12:27:07 -07:00
Eddie Hung
1a49cf29d8
parse_aiger() to rename all $lut cells after "clean"
2019-04-10 14:02:23 -07:00
Zachary Snow
5855024ccc
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 12:28:32 -04:00
Eddie Hung
36efec01b8
Fix spacing
2019-04-08 16:37:22 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Clifford Wolf
dfb242c905
Add "read_ilang -lib"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-05 17:31:49 +02:00
Clifford Wolf
584d2030bf
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-29 16:32:44 +01:00
Clifford Wolf
7682629b79
Add "read -verific" and "read -noverific"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 14:03:35 +01:00
Clifford Wolf
c863796e9f
Fix "verific -extnets" for more complex situations
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:17:46 +01:00
Clifford Wolf
638be461c3
Fix mem2reg handling of memories with upto data ports, fixes #888
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:21:17 +01:00
Clifford Wolf
da42f10765
Improve "read_verilog -dump_vlog[12]" handling of upto ranges
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:20:16 +01:00
Clifford Wolf
9b0e7af6d7
Improve read_verilog debug output capabilities
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 20:52:29 +01:00
Eddie Hung
02e8dc7ad2
Merge https://github.com/YosysHQ/yosys into read_aiger
2019-03-19 08:52:31 -07:00
Eddie Hung
3e89cf68bd
Add author name
2019-03-19 08:52:06 -07:00
Zachary Snow
a5f4b83637
fix local name resolution in prefix constructs
2019-03-18 20:43:20 -04:00
Clifford Wolf
17caaa3fa8
Improve handling of "full_case" attributes
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 17:51:21 +01:00
Clifford Wolf
d25a0c8ade
Improve handling of memories used in mem index expressions on LHS of an assignment
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
Clifford Wolf
a4ddc569b4
Remove outdated "blocking assignment to memory" warning
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:10:55 +01:00
Clifford Wolf
ab5b50ae3c
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:09:47 +01:00
Clifford Wolf
b02d9c2634
Fix handling of cases that look like sva labels, fixes #862
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-10 16:27:18 -07:00
Clifford Wolf
cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels
...
Add support for using SVA labels in yosys-smtbmc console output
2019-03-09 11:14:57 -08:00
Clifford Wolf
e7a34d342e
Also add support for labels on sva module items, fixes #699
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-08 22:55:09 -08:00
Eddie Hung
ee013fba54
Update help message for -chparam
2019-03-09 01:56:16 +00:00
Eddie Hung
2aa3903757
Add -chparam option to verific command
2019-03-09 01:54:01 +00:00
Eddie Hung
1dc060f32e
Fix spelling
2019-03-09 00:43:50 +00:00
Clifford Wolf
a330c68363
Fix handling of task output ports in clocked always blocks, fixes #857
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 22:44:37 -08:00
Clifford Wolf
22ff60850e
Add support for SVA labels in read_verilog
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 11:17:32 -08:00
Clifford Wolf
cda37830b0
Add hack for handling SVA labels via Verific
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 10:52:44 -08:00
Clifford Wolf
52f80718a7
Merge pull request #848 from YosysHQ/clifford/fix763
...
Fix error for wire decl in always block, fixes 763
2019-03-02 16:32:58 -08:00
Clifford Wolf
ae9286386d
Only run derive on blackbox modules when ports have dynamic size
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 12:36:46 -08:00
Clifford Wolf
3a51714451
Fix error for wire decl in always block, fixes #763
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 11:56:44 -08:00
Clifford Wolf
ce6695e22c
Fix $global_clock handling vs autowire
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 10:38:13 -08:00
Clifford Wolf
5d93dcce86
Fix $readmem[hb] for mem2reg memories, fixes #785
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 09:58:20 -08:00
Clifford Wolf
7cfae2c52f
Use mem2reg on memories that only have constant-index write ports
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 13:35:09 -08:00
Clifford Wolf
60e3c38054
Improve "read" error msg
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:34:42 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
da076344cc
parse_xaiger() to really pass single and multi-bit inout tests
2019-02-26 12:04:45 -08:00
Eddie Hung
8f02c846f6
parse_xaiger() to cope with multi bit inouts
2019-02-26 11:37:34 -08:00
Eddie Hung
316232a7dd
parse_xaiger() to untransform $inout.out output ports
2019-02-25 18:40:23 -08:00
Eddie Hung
721f6a14fb
read_aiger to accept empty string for clk_name, passable only if no latches
2019-02-25 15:34:02 -08:00
Clifford Wolf
1816fe06af
Fix handling of defparam for when default_nettype is none
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
Clifford Wolf
a516b4fb5a
Check if Verific was built with DB_PRESERVE_INITIAL_VALUE
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 19:51:30 +01:00
Eddie Hung
07036b8bf7
read_aiger to work with symbol table
2019-02-21 17:01:07 -08:00
Eddie Hung
085ed9f487
Add attribution
2019-02-21 14:40:13 -08:00
Eddie Hung
3307295488
Merge branch 'read_aiger' into xaig
2019-02-21 14:27:32 -08:00
Clifford Wolf
23148ffae1
Fixes related to handling of autowires and upto-ranges, fixes #814
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
Clifford Wolf
974927adcf
Fix handling of expression width in $past, fixes #810
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:55:33 +01:00
Clifford Wolf
28fba903c5
Fix segfault in printing of some internal error messages
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:40:52 +01:00
Eddie Hung
9e299a0908
read_aiger to not do -purge for clean
2019-02-20 17:33:04 -08:00
Eddie Hung
32853b1f8d
lut/not/and suffix to be ${lut,not,and}
2019-02-20 16:30:30 -08:00
Eddie Hung
abc1c2672e
read_aiger to also rename 0 index lut when wideports
2019-02-20 16:17:22 -08:00
Eddie Hung
f9702a8abe
read_aiger: new naming fixes
2019-02-20 12:39:51 -08:00
Eddie Hung
83b66861e9
read_aiger to name wires with internal name, less likely to clash
2019-02-20 11:22:56 -08:00
Eddie Hung
7b026c4bc3
Same for ascii AIGERs too
2019-02-19 15:15:50 -08:00
Eddie Hung
d304882cba
read_aiger to cope with non-unique POs
2019-02-19 15:14:08 -08:00
Eddie Hung
e79df5e70e
read_aiger to create sane $lut names, and rename when renaming driving wire
2019-02-19 12:27:50 -08:00
Eddie Hung
0b1fc46ae3
Add comment
2019-02-19 10:24:55 -08:00
Eddie Hung
54f719f446
Get rid of boost dep, fix the FIXMEs for Win32?
2019-02-19 10:19:53 -08:00
Eddie Hung
843e7fc8a7
Fix for using POSIX basename
2019-02-19 09:02:37 -08:00
Eddie Hung
8e1dbfac3a
Missing OSX headers?
2019-02-17 20:59:53 -08:00
Eddie Hung
9268a271fb
read_aiger to ignore line after ands for ascii, not binary
2019-02-17 12:07:14 -08:00
Eddie Hung
03a533d102
Merge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 11:44:01 -08:00
Eddie Hung
82459c16c4
In read_xaiger, do not construct ConstEval for every LUT
2019-02-16 22:22:29 -08:00
Eddie Hung
f60cd4ff9b
read_aiger to ignore output = input of same wire; also create new output for different wire
2019-02-16 21:53:03 -08:00
Eddie Hung
1a25ec4baa
read_aiger to disable log_debug
2019-02-16 13:45:51 -08:00
Eddie Hung
8f36013fac
read_xaiger() to use f.read() not readsome()
2019-02-16 08:58:25 -08:00
Eddie Hung
7523c87780
read_aiger() to cope with constant outputs, mixed wideports, do cleaning
2019-02-16 08:44:11 -08:00
Eddie Hung
8d757224ee
read_aiger with more asserts, and call clean
2019-02-15 11:52:05 -08:00
Eddie Hung
c7ef3863f3
Leave FIXME for clean
2019-02-13 17:19:30 -08:00
Eddie Hung
396da54b52
Use module->addLut()
2019-02-13 17:08:32 -08:00
Eddie Hung
13bf036bd6
Use ConstEval to compute LUT masks
2019-02-13 17:00:00 -08:00
Eddie Hung
f0f5d8a5cc
Merge remote-tracking branch 'origin/read_aiger' into xaig
2019-02-13 14:09:36 -08:00
Eddie Hung
06cf0555ee
Merge https://github.com/YosysHQ/yosys into xaig
2019-02-13 14:08:31 -08:00
Clifford Wolf
807b3c7697
Fix sign handling of real constants
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-13 12:36:47 +01:00
Eddie Hung
e9df9a466a
Add support for read_aiger -wideports
2019-02-12 12:58:10 -08:00
Eddie Hung
06ba81d41f
Add support for read_aiger -map
2019-02-12 12:16:37 -08:00
Eddie Hung
77d3627753
Parse 'm' in xaiger
2019-02-12 09:36:22 -08:00
Eddie Hung
6faad18874
Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger
2019-02-12 09:21:46 -08:00
Eddie Hung
a2ae393811
Use module->add{Not,And}Gate() functions
2019-02-12 09:21:15 -08:00
Eddie Hung
0124512f28
Add read_xaiger
2019-02-11 15:19:17 -08:00
Eddie Hung
04c580fde7
Do not break for constraints
2019-02-11 13:28:00 -08:00
Eddie Hung
727ba52504
No increment line_count for binary ANDs
2019-02-11 13:24:21 -08:00
Eddie Hung
bb4164481d
Do not ignore newline after AND in binary AIG
2019-02-11 11:51:44 -08:00
Eddie Hung
8886fa5506
addDff -> addDffGate as per @daveshah1
2019-02-08 13:17:53 -08:00
Eddie Hung
afc3c4b613
Fix tabulation
2019-02-08 13:17:02 -08:00
Eddie Hung
aa66d8f12f
-module_name arg to go before -clk_name
2019-02-08 12:49:55 -08:00
Eddie Hung
391ec75b07
Add missing "[options]" to read_blif help
2019-02-08 12:41:39 -08:00
Eddie Hung
fb8ad440a3
Allow module name to be determined by argument too
2019-02-08 12:40:43 -08:00
Eddie Hung
f1befe1b44
Refactor into AigerReader class
2019-02-08 12:04:26 -08:00
Eddie Hung
2a8cc36578
Parse binary AIG files
2019-02-08 11:45:16 -08:00
Eddie Hung
09d758f0a3
Refactor to parse_aiger_header()
2019-02-08 10:54:31 -08:00
Eddie Hung
36c56bf412
Add comment
2019-02-08 08:37:44 -08:00
Eddie Hung
5e24251a61
Handle reset logic in latches
2019-02-08 08:37:18 -08:00
Eddie Hung
652e414392
Change literal vars from int to unsigned
2019-02-08 08:09:30 -08:00
Eddie Hung
fafa972238
Create clk outside of latch loop
2019-02-08 08:08:49 -08:00
Eddie Hung
02f603ac1a
Handle latch symbols too
2019-02-08 08:05:27 -08:00
Eddie Hung
5a593ff41c
Remove return after log_error
2019-02-08 08:04:48 -08:00
Eddie Hung
6dbeda1807
Add support for symbol tables
2019-02-08 08:03:40 -08:00
Eddie Hung
791f93181d
Stub for binary AIGER
2019-02-08 07:31:04 -08:00
Eddie Hung
40db2f2eb6
Refactor
2019-02-06 14:58:47 -08:00
Eddie Hung
cc0b723484
WIP
2019-02-06 12:19:48 -08:00
Clifford Wolf
17ceab92a9
Bugfix in Verilog string handling
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-05 12:10:24 +01:00
Clifford Wolf
6d1e7e9403
Remove -m32 Verific eval lib build instructions
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-04 15:03:49 +01:00
Clifford Wolf
1eb101a38a
Improve VerificImporter support for writes to asymmetric memories
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-02 15:33:43 +01:00
Clifford Wolf
50b09de033
Fix VerificImporter asymmetric memories error message
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-02 15:05:23 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Clifford Wolf
6dad191377
Add "read_ilang -[no]overwrite"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-23 15:45:09 +01:00
Clifford Wolf
fdf7c42181
Fix segfault in AST simplify
...
(as proposed by Dan Gisselquist)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 17:49:38 +01:00
Clifford Wolf
3d671630e2
Improve src tagging (using names and attrs) of cells and wires in verific front-end
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 16:01:22 +01:00
whitequark
4effb38e6d
read_ilang: allow slicing sigspecs.
2018-12-16 17:53:26 +00:00
Sylvain Munaut
58fb2ac818
verilog_parser: Properly handle recursion when processing attributes
...
Fixes #737
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-14 12:48:00 +01:00
Clifford Wolf
910d94b212
Verific updates
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:21:50 +01:00
Sylvain Munaut
86ce43999e
Make return value of $clog2 signed
...
As per Verilog 2005 - 17.11.1.
Fixes #708
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-24 18:49:23 +01:00
Clifford Wolf
5387ccb041
Set Verific flag vhdl_support_variable_slice=1
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-09 21:03:23 +01:00
Clifford Wolf
719e29404a
Allow square brackets in liberty identifiers
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-05 12:33:33 +01:00
Clifford Wolf
36ea98385f
Add warning for SV "restrict" without "property"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 15:57:17 +01:00
Clifford Wolf
64e0582c29
Various indenting fixes in AST front-end (mostly space vs tab issues)
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
ZipCPU
39f891aebc
Make and dependent upon LSB only
2018-11-03 13:39:32 -04:00
Clifford Wolf
d86ea6badd
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-01 15:25:24 +01:00
Clifford Wolf
5ab58d4930
Fix minor typo in error message
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-25 13:20:00 +02:00
Clifford Wolf
6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error
...
More meaningful SystemVerilog/Verilog parser error messages
2018-10-25 13:18:59 +02:00
Udi Finkelstein
536ae16c3a
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
...
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00
Clifford Wolf
23b69ca32b
Improve read_verilog range out of bounds warning
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-20 23:48:53 +02:00
Ruben Undheim
436e3c0a7c
Refactor code to avoid code duplication + added comments
2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
Ruben Undheim
d9a4381012
Fixed memory leak
2018-10-20 11:57:39 +02:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
...
Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
Clifford Wolf
93d99559ef
Merge pull request #664 from tklam/ignore-verilog-protect
...
Ignore protect endprotect
2018-10-18 10:52:07 +02:00
Clifford Wolf
6ca493b88c
Minor code cleanups in liberty front-end
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-17 12:23:36 +02:00
Clifford Wolf
8395c18cb5
Merge pull request #660 from tklam/parse-liberty-detect-ff-latch
...
Handling ff/latch in liberty files
2018-10-17 12:21:17 +02:00
Clifford Wolf
38dbb44fa0
Merge pull request #638 from udif/pr_reg_wire_error
...
Fix issue #630
2018-10-17 12:13:18 +02:00
argama
097da32e1a
ignore protect endprotect
2018-10-16 21:33:37 +08:00
Ruben Undheim
736105b046
Handle FIXME for modport members without type directly in front
2018-10-13 20:50:33 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
...
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
argama
455638e00d
detect ff/latch before processing other nodes
2018-10-14 01:42:48 +08:00
Ruben Undheim
a36d1701dd
Fix build error with clang
2018-10-12 22:14:49 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
...
This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Clifford Wolf
9850de405a
Improve Verific importer blackbox handling
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-07 19:48:55 +02:00
Clifford Wolf
4b0448fc2c
Fix compiler warning in verific.cc
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-05 09:26:10 +02:00
Tom Verbeure
cb214fc01d
Fix for issue 594.
2018-10-02 07:44:23 +00:00
Dan Gisselquist
62424ef3de
Add read_verilog $changed support
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-01 19:41:35 +02:00
Clifford Wolf
4d2917447c
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-30 18:44:07 +02:00
Clifford Wolf
9f9fe94b35
Fix handling of $past 2nd argument in read_verilog
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-30 18:43:35 +02:00
Udi Finkelstein
80a07652f2
Fixed issue #630 by fixing a minor typo in the previous commit
...
(as well as a non critical minor code optimization)
2018-09-25 00:32:57 +03:00
Clifford Wolf
8fde05dfa5
Add "read_verilog -noassert -noassume -assert-assumes"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-24 20:51:16 +02:00