15 Commits

Author	SHA1	Message	Date
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	7daad40ca4	Fixed counting verilog line numbers for "// synopsys translate_off" sections	2014-07-30 20:18:48 +02:00
Clifford Wolf	e605af8a49	Fixed Verilog pre-processor for files with no trailing newline	2014-07-29 20:14:25 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	02e6f2c5be	Added Verilog support for "`default_nettype none"	2014-02-17 14:28:52 +01:00
Clifford Wolf	13359d65ba	Fixed parsing of verilog macros at end of line	2014-01-18 19:22:20 +01:00
Clifford Wolf	1dcbba1abf	Fixed parsing of non-arg macro calls followed by "("	2013-12-27 16:25:27 +01:00
Clifford Wolf	72026a934e	Fixed parsing of macros with no arguments and expansion text starting with "("	2013-12-27 15:05:52 +01:00
Clifford Wolf	fbd06a1afc	Added elsif preproc support	2013-12-18 13:41:36 +01:00
Clifford Wolf	921064c200	Added support for macro arguments	2013-12-18 13:21:02 +01:00
Clifford Wolf	a362fd81ae	Fixed O(n^2) performance bug in verilog preprocessor	2013-11-22 14:08:43 +01:00
Clifford Wolf	e4429c480e	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
Johann Glaser	a99c224157	Added support for include directories with the new '-I' argument of the ... 'read_verilog' command	2013-08-20 15:48:16 +02:00
Johann Glaser	10a195c0a1	added option '-Dname[=definition]' to command 'read_verilog'	2013-05-19 17:07:52 +02:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00