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878 Commits

Author SHA1 Message Date
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf 0eaab6cd1d Add missing <deque> include (MSVC build fix) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 15:21:59 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
David Shah 459d367913 ecp5: Adding synchronous set/reset support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-14 16:18:01 +02:00
Clifford Wolf 675a44b41a Be slightly less aggressive in "deminout" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-19 14:29:38 +02:00
Robert Ou 9763e4d830 Fix infinite loop in abc command under emscripten 2018-05-18 22:42:39 -07:00
Robert Ou bfce3a7479 Add an option to statically link abc into yosys 
This is currently incomplete because the output filter no longer works.
 2018-05-18 22:35:28 -07:00
Clifford Wolf fe80b39f56 Fix iopadmap for loops between tristate IO buffers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 14:02:27 +02:00
Clifford Wolf edd297fb1c Fix iopadmap for cases where IO pins already have buffers on them 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 13:13:43 +02:00
Clifford Wolf 145c685de0 Add ABC FAQ to "help abc" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-04 21:59:31 +02:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Clifford Wolf 705c366a91 Added missing dont_use handling for SR FFs to dfflibmap 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-05 11:01:45 +02:00
Clifford Wolf a74f805ba0 Fix handling of src attributes in flatten 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-10 13:55:30 +01:00
Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-09 18:42:19 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Staf Verhaegen 92eb841f0a Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:37:17 +00:00
Clifford Wolf 7c57d8fbb4 Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
Andrew Zonenberg 2b65b65d70 Added missing "break" 2017-09-15 17:54:52 -07:00
Andrew Zonenberg 7b3966714c Implemented off-chain support for extract_reduce 2017-09-15 13:59:18 -07:00
Andrew Zonenberg 3404934c9c extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored. 2017-09-15 13:59:05 -07:00
Clifford Wolf ce78717e36 Merge pull request #412 from azonenberg/reduce-fixes 
extract_reduce: Fix segfault on "undriven" inputs
 2017-09-14 22:36:25 +02:00
Robert Ou ab1bf8d661 extract_reduce: Fix segfault on "undriven" inputs 
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
 2017-09-14 12:54:44 -07:00
Andrew Zonenberg 367d6b2194 Fixed bug where counter extraction on non-GreenPAK devices incorrectly handled parallel counter output 2017-09-14 10:27:10 -07:00
Andrew Zonenberg c8f2f082c6 Added support for inferring counters with reset to full scale instead of zero 2017-09-14 10:26:43 -07:00
Andrew Zonenberg 122532b7e1 Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
Andrew Zonenberg 0484ad666d Added support for inferring counters with active-low reset 2017-09-14 10:26:21 -07:00
Andrew Zonenberg a84172b23b Initial support for extraction of counters with clock enable 2017-09-14 10:26:10 -07:00
Andrew Zonenberg c4a70a8cc3 Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters. 2017-09-14 10:25:51 -07:00
Clifford Wolf 7d41c5e177 Further improve extract_fa (but still buggy) 2017-09-02 16:39:17 +02:00
Clifford Wolf 18609f3df8 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-09-01 12:35:09 +02:00
Clifford Wolf 8a66bd30c6 Update more stuff to use get_src_attribute() and set_src_attribute() 2017-09-01 12:26:55 +02:00
Jason Lowdermilk 8dc6083de7 updated to use get_src_attribute() and set_src_attribute(). 2017-08-31 14:51:56 -06:00
Andrew Zonenberg ed1e3ed39b extract_counter: Added optimizations to remove unused high-order bits 2017-08-30 18:15:12 -07:00
Andrew Zonenberg 634f18be96 extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos 2017-08-30 16:28:25 -07:00
Jason Lowdermilk 32c0f1193e Add support for source line tracking through synthesis phase 2017-08-29 14:46:35 -06:00
Andrew Zonenberg 3fc1b9f3fd Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells. 2017-08-28 22:18:57 -07:00
Andrew Zonenberg 46b01f05bb Refactored extract_counter to be generic vs GreenPAK specific 2017-08-28 22:18:47 -07:00
Andrew Zonenberg b5c15636c5 Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass 2017-08-28 22:18:34 -07:00
Clifford Wolf 908f34aafc Rename recover_reduce to extract_reduce, fix args handling 2017-08-28 19:52:06 +02:00
Clifford Wolf 3aad3ed3da Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azonenberg-recover-reduce 2017-08-28 19:46:17 +02:00
Clifford Wolf ebbb0e9479 Further improve extract_fa pass 2017-08-28 19:43:26 +02:00
Robert Ou 849b885775 recover_reduce: Update documentation 
The documentation now describes the commands performed in the deleted
recover_reduce script.
 2017-08-27 02:19:19 -07:00
Robert Ou 74d0f17fd4 recover_reduce: Reindent using tabs 2017-08-27 02:12:41 -07:00
Robert Ou 8a5887464c recover_reduce: Rename recover_reduce_core to recover_reduce 
Clifford has commented on PR #387 stating that he does not like the
driver script and would prefer to only have the core script with
appropriate notes in the documentation.

Also rename to .cc (rather than .cpp) for consistency.
 2017-08-27 02:01:32 -07:00
Robert Ou 99dad40ed0 recover_reduce: Add driver script for the $reduce_* recover feature 
Conflicts:
	passes/techmap/Makefile.inc
 2017-08-27 01:57:20 -07:00
Robert Ou 8b7dc792ee recover_reduce_core: Finish implementing the core function 2017-08-27 01:56:49 -07:00
Robert Ou fa310c98f8 recover_reduce_core: Initial commit 
Conflicts:
	passes/techmap/Makefile.inc
 2017-08-27 01:56:49 -07:00
Clifford Wolf 382cc90c65 Further improve extract_fa (seems to be fully functional now) 2017-08-25 13:41:54 +02:00
Clifford Wolf 0bf612506c Rename "adders" to "extract_fa" 2017-08-25 12:04:40 +02:00
Clifford Wolf 15cdda7c4b Towards more generic "adder" function extractor 2017-08-23 14:20:10 +02:00
Clifford Wolf 51cbec7f75 Add experimental adders pass 2017-08-22 13:52:13 +02:00
Robert Ou 9a64ba3338 abc: Allow +/ filenames in the abc command 2017-08-14 12:11:11 -07:00
Clifford Wolf 5c09f24e48 Fix typo in "abc" pass help message 2017-07-29 16:21:58 +02:00
Clifford Wolf b3bc7068d1 Fix handling of empty cell port assignments (i.e. ignore them) 2017-07-21 19:32:31 +02:00
Clifford Wolf 155a80dfb7 Fix handling of init values in "abc -dff" and "abc -clk" 2017-06-20 15:32:23 +02:00
Clifford Wolf f6421c83a2 Switched abc "clock domain not found" error to log_cmd_error() 2017-06-20 04:22:34 +02:00
Clifford Wolf fad52abf70 Add aliases for common sets of gate types to "abc -g" 2017-05-24 11:39:05 +02:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
Clifford Wolf cf25dc9ce7 Copy attributes to _TECHMAP_REPLACE_ cells 2017-02-16 12:28:42 +01:00
Clifford Wolf db7314bc02 Fix techmap for inout ports connected to inout ports 2017-02-13 16:55:25 +01:00
Clifford Wolf 8927e19b13 Update ABC scripts to use "&nf" instead of "map" 2017-02-01 11:15:20 +01:00
Clifford Wolf 55785a96eb Improved ABC default scripts 2016-11-19 18:20:54 +01:00
Clifford Wolf 74702b04c2 Build fixes for VS 2015 2016-10-16 20:37:02 +02:00
Clifford Wolf e4c5ee9b89 Avoid using strcasecmp() 2016-10-14 18:20:36 +02:00
Clifford Wolf ffbb4e992e Added MEMID handling to "flatten" pass 2016-10-14 10:36:37 +02:00
Clifford Wolf ee91350add Added "zinit" pass 2016-10-12 12:05:19 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf d8ad889594 Bugfix in techmap parameter handling 2016-09-14 20:46:54 +02:00
Clifford Wolf 73b7232ec8 Fixed some compiler warnings in attrmap command 2016-08-10 13:44:08 +02:00
Clifford Wolf b0aab4e304 Added "attrmap" command 2016-08-09 19:56:55 +02:00
Clifford Wolf 3c6d31fd06 Added "attrmvcp" pass 2016-08-09 11:18:48 +02:00
Clifford Wolf 9d15529214 Undo "preserve wire attributes in iopadmap" change (it was OK before) 2016-08-08 11:47:35 +02:00
Clifford Wolf 90c17aad56 preserve wire attributes in iopadmap 2016-08-06 13:24:59 +02:00
Clifford Wolf 5d6765a9d2 Added "insbuf" command 2016-08-02 10:37:19 +02:00
Clifford Wolf 541083cf32 Bugfix in "abc -script" handling 2016-06-19 22:19:19 +02:00
Clifford Wolf ca91bccb6b Added "deminout" 2016-06-19 13:08:16 +02:00
Clifford Wolf 3380281e15 Added "dc2" to default ABC scripts 2016-06-17 20:15:35 +02:00
Clifford Wolf f498204ae4 Added "abc -I <num> -P <num>" 2016-06-17 19:39:35 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf c3365034e9 Updated ABC to hg rev b5df6e2b76f0 2016-06-17 11:16:31 +02:00
Clifford Wolf 99edf24966 Added "nlutmap -assert" 2016-06-09 11:47:41 +02:00
Clifford Wolf c3f6e0ea85 Added support for "keep" attribute to shregmap 2016-05-07 09:33:16 +02:00
Clifford Wolf aadca148da Fixed preservation of important attributes in techmap 2016-05-06 13:59:30 +02:00
Andrew Zonenberg 3486637b19 Changed port names in greenpak shregmap 2016-05-04 17:04:50 -07:00
Clifford Wolf 9647dc3c07 Added tristate buffer support to iopadmap 2016-05-04 22:48:02 +02:00
Clifford Wolf 658f93663b Fixed iopadmap attribute handling 2016-05-04 10:48:23 +02:00
Clifford Wolf 096c25d29d Improvements in greenpak4 shreg mapping 2016-04-23 23:10:13 +02:00
Andrew Zonenberg 7f16784f3c Merge https://github.com/cliffordwolf/yosys 2016-04-23 12:22:08 -07:00
Clifford Wolf e13c66122e Added "shregmap -zinit" for greenpak4 tech 2016-04-23 20:20:21 +02:00
Andrew Zonenberg 2849fd486e Fixed typo in help text 2016-04-22 23:01:39 -07:00
Clifford Wolf 7311be4028 Added "shregmap -tech greenpak4" 2016-04-22 19:42:08 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf f1fa757d0e Added "shregmap -params" 2016-04-18 11:58:21 +02:00
Clifford Wolf 525651c8f6 Added "shregmap -zinit" and "shregmap -init" 2016-04-18 11:44:10 +02:00
Clifford Wolf ce7c980ec7 Improvements in "shregmap" 2016-04-17 15:37:22 +02:00
Clifford Wolf de647a390c Added "shregmap" pass 2016-04-16 23:20:49 +02:00
Clifford Wolf fbdb8e7b3e Fixed copy&paste error in log message in lut2mux 2016-04-16 23:20:34 +02:00
Clifford Wolf 6041f780c3 Prefer noninverting FFs in dfflibmap 2016-04-05 12:51:04 +02:00
Clifford Wolf 9717495401 Fixed handling of inverters (aka 1-input luts) in nlutmap 2016-03-23 08:56:08 +01:00
Clifford Wolf bb9374b67c Improvements in ABCEXTERNAL handling 2016-03-19 20:02:40 +01:00
Sergey Kvachonok 2656b2c55a Support calling out to an external ABC. 
$ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install

configures yosys to use an external ABC executable instead of
building and installing the in-tree ABC copy (yosys-abc).
 2016-03-19 18:36:18 +03:00
Clifford Wolf c4aaed099f Using "mfs" and "lutpack" in ABC lut mapping 2016-03-07 11:14:11 +01:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf 801c022457 Improved dffsr2dff pass 2016-02-02 19:42:49 +01:00
Clifford Wolf d69395ca08 Added dffsr2dff 2016-02-02 17:19:01 +01:00
Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
Clifford Wolf 9251553592 Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs) 2016-02-01 11:49:11 +01:00
Clifford Wolf 71f418c468 More clang sanitizer stuff 2016-01-31 19:55:48 +01:00
Clifford Wolf d98d99aec6 Added "abc -g" 2015-11-10 11:10:11 +01:00
Marcus Comstedt 8c2bdef36d Fix a segfault in dffinit when the value has too few bits 
The code was already trying to add the required number of bits, but
fell one short of the mark.
 2015-11-08 19:16:56 +01:00
Clifford Wolf f401eeb0cf Bugfix in mapping $tribuf to $_TBUF_ 2015-11-05 12:37:43 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 6fe48cf41e equiv_purge bugfix, using SigChunk in Yosys namespace 2015-10-24 19:09:45 +02:00
Clifford Wolf eb1e3caae7 Fixed "flatten" for unconnected inout ports 2015-10-13 10:30:23 +02:00
Clifford Wolf 598a475724 Added nlutmap 2015-09-18 21:57:34 +02:00
Clifford Wolf c851f51656 Added lut2mux pass 2015-09-18 21:55:48 +02:00
Clifford Wolf db548800b6 Added buffer detection to "abc -lut" 2015-09-18 20:12:56 +02:00
Clifford Wolf 452d4bf741 Added support for "dfflibmap -liberty +/..." 2015-09-18 11:55:57 +02:00
Clifford Wolf 24e7cf89bc Fixed iopadmap help message 2015-08-31 16:49:42 +02:00
Clifford Wolf 92dce21f6e Using dict<> and pool<> in alumacc pass 2015-08-31 16:26:01 +02:00
Clifford Wolf f43815054e Properly clean up unused "init" attributes 2015-08-18 13:50:15 +02:00
Clifford Wolf 9c33172ece Added tribuf command 2015-08-16 12:55:25 +02:00
Clifford Wolf ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf 0350074819 Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf 80910d13a6 Merge branch 'master' of github.com:cliffordwolf/yosys 2015-08-13 09:52:06 +02:00
Clifford Wolf 08ad5409a2 Some ASCII encoding fixes (comments and docs) by Larry Doolittle 2015-08-13 09:30:20 +02:00
Clifford Wolf e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf 3860c9a9f2 Fixed flatten $meminit handling 2015-07-30 21:43:41 +02:00
Clifford Wolf ad919ae4e3 Fixed techmap processes error msg 2015-07-18 12:16:27 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 1ae360cf72 AigMaker refactoring 2015-06-10 23:00:12 +02:00
Clifford Wolf 56d4822719 Renamed "aig" to "aigmap" 2015-06-10 07:24:26 +02:00
Clifford Wolf 85287295b2 Fixed cellaigs port extending 2015-06-10 07:16:30 +02:00
Clifford Wolf 66f9ee412a Added "aig" pass 2015-06-09 22:33:26 +02:00
Clifford Wolf 522705cc28 Added liberty dont_use support to dfflibmap 2015-05-31 07:51:12 +02:00
Clifford Wolf 9f772eb970 Improved "flatten" handlings of inout ports 2015-05-23 10:14:53 +02:00
Clifford Wolf e5116eeb77 Generalized blifparse API 2015-05-17 15:10:37 +02:00
Clifford Wolf 7dad017c9c abc/blifparse files reorganization 2015-05-17 14:44:28 +02:00
Clifford Wolf 794d22969d Added simplemap $lut support 2015-04-27 10:16:07 +02:00
Clifford Wolf 49859393bb Improved attributes API and handling of "src" attributes 2015-04-24 22:04:05 +02:00
Clifford Wolf 8cdbcf6859 Bugfix for $_DFF_?_ in "dff2dffe -direct-match" 2015-04-17 21:35:59 +02:00
Clifford Wolf e050467b89 Improved "maccmap" help message 2015-04-16 18:23:43 +02:00
Clifford Wolf dc30b034f7 Fixed "dff2dffe -direct-match" 2015-04-16 11:47:59 +02:00
Clifford Wolf f80d020f17 Added "dff2dffe -direct-match" 2015-04-16 11:30:17 +02:00
Clifford Wolf be7b9b34ca techmap code cleanup 2015-04-09 12:02:26 +02:00
Clifford Wolf 21a1cc1b60 Added support for "file names with blanks" 2015-04-08 12:14:34 +02:00
Clifford Wolf aa0ab975b9 Removed "techmap -share_map" (use "-map +/filename" instead) 2015-04-08 12:13:53 +02:00
Clifford Wolf 724cead61d Added "pmuxtree" command 2015-04-07 20:27:10 +02:00
Clifford Wolf 590f74d8f0 Added decoder generation to "muxcover" 2015-04-07 18:03:27 +02:00
Clifford Wolf f7fb21f185 Added "muxcover" command 2015-04-07 15:42:25 +02:00
Clifford Wolf c52a4cdeed Added "dffinit", Support for initialized Xilinx DFF 2015-04-04 19:00:15 +02:00
Clifford Wolf 8b1e0bdd9e Fixed handling of quotes in liberty parser 2015-03-18 16:03:19 +01:00
Clifford Wolf 27a918eadf Merge branch 'master' of github.com:cliffordwolf/yosys 2015-02-25 23:01:54 +01:00
Clifford Wolf 331f8b8d0b Bugfix in iopadmap 2015-02-25 23:01:42 +01:00
Clifford Wolf 3fe18c26cd Added "keep_hierarchy" attribute 2015-02-25 12:46:00 +01:00
Clifford Wolf 49dd9c713f Fixed "flatten" for non-pre-derived modules 2015-02-21 15:01:13 +01:00
Clifford Wolf f778a4081c Catch constants assigned to cell outputs in "flatten" 2015-02-21 11:21:28 +01:00
Clifford Wolf f41378af8c Fixed clang (svn trunk) warnings 2015-02-18 14:54:22 +01:00
Clifford Wolf 3216f9420e More emscripten stuff, Added example app 2015-02-15 12:09:30 +01:00
Clifford Wolf 2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf 8658eed52a Added support for memories to flatten (techmap) 2015-01-17 20:46:52 +01:00
Clifford Wolf 8ce8a230f4 Bugfix in dff2dffe 2015-01-16 17:51:17 +01:00
Clifford Wolf 9065fb25cc Fixed handling of foo.__TECHMAP_... 2015-01-15 13:36:57 +01:00
Clifford Wolf 4a0b3a5423 Various small improvements to synth_xilinx 2015-01-06 14:37:50 +01:00
Clifford Wolf c64b1de11d Fixed build with SMALL=1 2014-12-30 11:41:24 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf 170788a3de Fixed simplemap for $ne cells with output width > 1 2014-12-25 16:41:20 +01:00
Clifford Wolf aad195b88c Added "dfflibmap -prepare" help 2014-12-24 12:56:05 +01:00
Clifford Wolf 35f5aa300f Added "dfflibmap -prepare" 2014-12-24 12:19:20 +01:00
Clifford Wolf 032ce573a3 Added "dff2dffe -direct" for direct gate mapping 2014-12-24 11:39:15 +01:00
Clifford Wolf 8c1a72c2a4 Added "dff2dffe -unmap" 2014-12-24 11:09:01 +01:00
Clifford Wolf afcacd6437 Added support for gate-level cells in dff2dffe 2014-12-24 10:49:54 +01:00
Clifford Wolf 4aa9fbbf3f Improvements in simplemap api, added $ne $nex $eq $eqx support 2014-12-24 10:49:24 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 032511fac8 Added functionality to dff2dffe pass 2014-12-08 15:38:58 +01:00
Clifford Wolf 97487fee32 Added skeleton dff2dffe pass 2014-12-08 14:10:52 +01:00
Clifford Wolf f1764b4fe9 Added $dffe cell type 2014-12-08 10:50:19 +01:00
Clifford Wolf 546e8b5fe7 Improved TopoSort determinism 2014-11-07 15:21:03 +01:00
Clifford Wolf 84ffe04075 Fixed various VS warnings 2014-10-18 15:20:38 +02:00
Clifford Wolf 973d376733 Added genfiles.zip to MXE "make dist" 2014-10-17 12:11:15 +02:00
Clifford Wolf c21c9dab1e Removed CHECK() macro from libparse.cc (was using non-std c features) 2014-10-13 17:22:06 +02:00
Clifford Wolf 54bf3a95dd More Win32 build fixes 2014-10-10 18:34:19 +02:00
Clifford Wolf bbd808072b Added format __attribute__ to stringf() 2014-10-10 17:22:08 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf ccf7b2e342 Added mxe-based cross build for win32 2014-10-09 10:50:44 +02:00
Clifford Wolf 696d7ed40e Fixes in "hilomap" help message 2014-10-08 21:38:37 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf b86410b2ab More aggressive $macc merging in alumacc 2014-09-15 12:42:11 +02:00
Clifford Wolf b470c480e9 Added the obvious optimizations to alumacc $macc generator 2014-09-15 12:22:03 +02:00
Clifford Wolf fcbda07411 Improved maccmap tree bit packing 2014-09-15 12:00:19 +02:00
Clifford Wolf 7e156a5419 Fixed techmap_wrap for techmap_celltype 2014-09-14 15:34:36 +02:00
Clifford Wolf 014bb34e0e Various fixes/cleanups in alumacc and maccmap 2014-09-14 14:49:53 +02:00
Clifford Wolf 124e759280 Added techmap_wrap attribute 2014-09-14 14:49:26 +02:00
Clifford Wolf b34ca15185 alumacc fix for $pos cells 2014-09-14 14:00:14 +02:00
Clifford Wolf 0df1d9ad72 Extract $alu cells in alumacc 2014-09-14 13:23:44 +02:00
Clifford Wolf 7b16c63101 Merge $macc cells in alumacc pass 2014-09-14 11:21:37 +02:00
Clifford Wolf 0b72f0acb1 Basic $macc extract in alumacc 2014-09-14 10:45:28 +02:00
Clifford Wolf ff157fb74f alumacc skeleton 2014-09-14 10:02:00 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf 1a88e47396 Trim msb/lsb zero bits from full adder in maccmap 2014-09-08 11:21:58 +02:00
Clifford Wolf c50b841b29 Added 'techmap_maccmap' techmap attribute 2014-09-07 18:23:37 +02:00
Clifford Wolf 015dcdc84c Added "maccmap" command 2014-09-07 18:23:04 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf 826fdb34d8 Added "techmap -autoproc" 2014-09-01 15:36:29 +02:00
Clifford Wolf d148b0af0d Fixed inserting of Q-inverters in dfflibmap 2014-08-27 19:44:12 +02:00
Clifford Wolf c642dd0b3e Only call proc_share_dirname() in techmap when necessary 2014-08-23 15:32:00 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf 410d043dd8 Renamed toposort.h to utils.h 2014-08-17 00:55:35 +02:00
Clifford Wolf 674f421b47 Bugfix in iopadmap 2014-08-15 14:29:42 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00
Clifford Wolf d320e75087 document "techmap -map %<design-name>" 2014-08-15 02:01:30 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 014a41fcf3 Implemented recursive techmap 2014-08-03 12:40:43 +02:00
Clifford Wolf 08ec33a5e5 Implemented simplemap support for "techmap -extern" 2014-08-02 21:55:13 +02:00
Clifford Wolf b6acbc82e6 Bugfix in "techmap -extern" 2014-08-02 20:54:30 +02:00
Clifford Wolf 04727c7e0f No implicit conversion from IdString to anything else 2014-08-02 18:58:40 +02:00
Clifford Wolf 768eb846c4 More bugfixes related to new RTLIL::IdString 2014-08-02 18:14:21 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 6ca0c569d9 Added "techmap -assert" 2014-07-31 02:21:41 +02:00
Clifford Wolf 2541489105 Added techmap CONSTMAP feature 2014-07-30 22:04:30 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 8b0f50792c Added techmap -extern 2014-07-27 21:31:18 +02:00
Clifford Wolf 5da343b7de Added topological sorting to techmap 2014-07-27 16:43:39 +02:00
Clifford Wolf 49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf 45b4154b37 Added "make SMALL=1" 2014-07-24 19:03:57 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 361e0d62ff Replaced depricated NEW_WIRE macro with module->addWire() calls 2014-07-21 12:42:02 +02:00
Clifford Wolf 1d88f1cf9f Removed deprecated module->new_wire() 2014-07-21 12:35:06 +02:00
Clifford Wolf 8d04ca7d22 Added call_on_selection() and call_on_module() API 2014-07-20 15:33:06 +02:00
Clifford Wolf b76bf05cda Added support for "blackbox" attribute to iopadmap 2014-07-17 08:59:07 +02:00
Clifford Wolf 64a6906cc4 Added support for "blackbox" attribute to flatten/techmap 2014-07-17 08:58:51 +02:00
Johann Glaser 684c85902d be more verbose when techmap yielded processes 2014-05-26 17:13:41 +02:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Siesh1oo 8127d5e8c3 - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). 
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
 - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
 2014-03-12 23:17:14 +01:00
Clifford Wolf 9087ece97c OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:52:37 +01:00
Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf fcae92868d Fixed dumping of timing() { .. } block in libparse 2014-03-09 15:16:07 +01:00
Clifford Wolf 1ecaf1bb76 Added techmap -max_iter option 2014-03-06 12:15:17 +01:00
Clifford Wolf 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap 2014-02-20 23:42:07 +01:00
Clifford Wolf 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." 2014-02-20 23:31:13 +01:00
Clifford Wolf 236fc4209c Added "extract -map %<design_name>" 2014-02-20 23:30:15 +01:00
Clifford Wolf a71d09421d Added techmap support for _TECHMAP_CONNMAP_*_ 2014-02-18 19:51:00 +01:00
Clifford Wolf ca53ef5098 Better preserve wires when flattening (in comparison to techmap) 2014-02-17 09:44:39 +01:00
Clifford Wolf 6d63f39eb6 Added some additional checks to techmap 2014-02-16 22:18:06 +01:00
Clifford Wolf a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap 2014-02-16 21:58:59 +01:00
Clifford Wolf d3dc22a90f Added recursion support to techmap 2014-02-16 17:16:44 +01:00
Clifford Wolf 623a68f528 Added iopadmap -bits 2014-02-15 21:59:26 +01:00
Clifford Wolf cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff 2014-02-15 16:34:12 +01:00
Clifford Wolf 6644f80d97 Moved some passes to other source directories 2014-02-08 14:39:15 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf c13c5b9b7b Changed techmap description from "simple" to "generic" 2014-02-06 13:10:06 +01:00
Clifford Wolf c1ed2607fb Added support for // comments in liberty parser 2014-01-25 06:32:16 +01:00
Clifford Wolf 32a91458a7 Added hilomap command 2014-01-19 21:58:58 +01:00
Clifford Wolf 9a00980129 renamed LibertyParer to LibertyParser 2014-01-14 18:57:47 +01:00
Clifford Wolf c1da7661a5 Added "+" to list of liberty token characters 2014-01-14 18:56:29 +01:00
Clifford Wolf bf607df6d5 Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen) 2013-12-29 17:39:49 +01:00
Clifford Wolf fe8ec32a1c Added new cell types to manual 2013-12-28 12:10:32 +01:00
Clifford Wolf c69c416d28 Added $bu0 cell (for easy correct $eq/$ne mapping) 2013-12-28 12:02:14 +01:00
Clifford Wolf 334b0cc803 Fixed dfflibmap for unused output ports 2013-12-21 20:47:22 +01:00
Clifford Wolf 8856cec308 Now prefer smallest cells in dfflibmap 2013-12-21 08:42:37 +01:00
Clifford Wolf 1fb29050e5 Cleanup of dfflibmap cellmap exploration code 2013-12-20 14:21:18 +01:00
Clifford Wolf eaf7d9675d Further improved dfflibmap cellmap exploration 2013-12-20 12:34:34 +01:00
Clifford Wolf 404bcc2d1e Fixed dfflibmap endless-loop bug 2013-12-20 12:13:51 +01:00
Clifford Wolf c904f5e197 Prefer non-inverted clocks in dfflibmap 2013-12-19 13:21:57 +01:00
Clifford Wolf f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf 76f7c10cfc Using simplemap mappers from techmap 2013-11-24 23:31:14 +01:00
Clifford Wolf 3ee33cbdaf Added simplemap pass 2013-11-24 22:52:30 +01:00
Clifford Wolf 8dafecd34d Added module->avail_parameters (for advanced techmap features) 2013-11-24 20:29:07 +01:00
Clifford Wolf 4011d47646 Added techmap -D and -I options 2013-11-24 20:04:48 +01:00
Clifford Wolf 20175afd29 Added "techmap -share_map" option 2013-11-24 19:50:25 +01:00
Clifford Wolf 609caa23b5 Implemented correct handling of signed module parameters 2013-11-24 17:17:21 +01:00
Clifford Wolf 72b35e0b99 Fixed "flatten" top-module detection: Only use on fully selected designs 2013-11-24 14:10:46 +01:00
Clifford Wolf 28093d9dd2 Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
Clifford Wolf 5f9c7fc6ea Improved handling of techmap special wires 2013-11-23 16:49:58 +01:00
Clifford Wolf 532091afcb Added more generic _TECHMAP_ wire mechanism to techmap pass 2013-11-23 15:58:06 +01:00
Clifford Wolf 295e352ba6 Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00
Clifford Wolf 378cc509cd Call internal checker more often 2013-11-10 23:24:21 +01:00
Clifford Wolf 0efe16f118 Added placeholder check to dfflibmap and cleaned up some other placeholder checks 2013-10-31 12:27:07 +01:00
Clifford Wolf ceb971eab9 Added support for i/o buffers to iopadmap 2013-10-26 22:27:40 +02:00
Clifford Wolf dd56004fc0 Added support for sr flip-flops to dfflibmap 2013-10-24 18:20:06 +02:00
Clifford Wolf e679a5d046 Fixed handling of boolean attributes (passes) 2013-10-24 11:37:54 +02:00
Clifford Wolf 9bc703b964 Improved way of connecting ports in techmap pass 2013-10-17 22:19:38 +02:00
Clifford Wolf 96e7abad48 Added iopadmap pass 2013-10-16 16:16:06 +02:00
Clifford Wolf b6db2d9b33 Moved dfflibmap from passes/dfflibmap to passes/techmap 2013-10-16 15:32:26 +02:00
Clifford Wolf 288ba9618a Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00
Clifford Wolf 376150c926 Added techmap -opt mode 2013-08-09 15:20:22 +02:00
Clifford Wolf 5f2c5f9017 Fixed techmap/flatten for positional module arguments 2013-05-26 12:21:17 +02:00
Clifford Wolf e04d88cf22 Added missing newline to some error messages 2013-05-23 11:19:33 +02:00
Clifford Wolf 83c743f717 Added support for const cell inputs in techmap 2013-04-27 18:30:29 +02:00
Clifford Wolf b1cb4d7871 Added "flatten" pass 2013-04-26 14:40:45 +02:00
Clifford Wolf 8edf4f378a Added proper TECHMAP_FAIL support and added support for the celltype attribute in the map file 2013-03-28 10:12:50 +01:00
Clifford Wolf 020a35d11e Removed date from auto-generated passes/techmap/stdcells.inc 2013-03-18 07:32:33 +01:00
Johann Glaser 3b8ebd694d add header to autogenerated file on its origin 2013-03-18 07:28:31 +01:00
Johann Glaser cd8008bda0 fixed typos 2013-03-18 07:28:31 +01:00
Clifford Wolf b96ffed69b Automatically select new objects in abc and techmap passes 2013-03-08 09:16:25 +01:00
Clifford Wolf 7fccad92f7 Added more help messages 2013-03-01 00:36:19 +01:00
Clifford Wolf 6543917fb8 added .gitignore files 2013-01-05 11:19:11 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00