The make targets echo-yosys-ver, echo-git-ver and echo-abc-rev can be
used to programmatically extract contents of make variables for external
scripts. Unfortunately, when a Makefile.conf exists, its contents would
also be echoed, making the output almost unusable. This patch
selectively disables this functionality for these special targets.
A few passes included the same list of FF cell types. Make it a global
const instead.
The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
This commit reduces space and time overhead for writable memories
to O(write port count) in both cases; implements handling for write
port priorities; and simplifies runtime representation of memories.
Hierarchical design simulations are generally much slower, but this
comes with a major increase in flexibility:
1. Since the `flatten` pass currently does not support flattening
of designs with processes, this is the only way to simulate such
designs with cxxrtl.
2. Support for hierarchy paves way for simulation black boxes,
which are necessary for e.g. replacing PHYs with C++ code that
integrates with the host system.
After this commit, if NDEBUG is not defined, out-of-bounds accesses
cause assertion failures for reads and writes. If NDEBUG is defined,
out-of-bounds reads return zeroes, and out-of-bounds writes are
ignored.
This commit also adds support for memories that start with a non-zero
index (`Memory::start_offset` in RTLIL).
This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.
In the past I was calling the ILANG_BACKEND::dump_const() to dump
values to an output stream. When these values were strings, the
function used to add quotes around them. The firrtl compiler, in turn,
escaped these quotes and the result was double-quoted strings which
were hard to read.
However I'm now calling design_entity->get_src_attribute() directly
and there is no additional quote being put around it, so we can
safely remove the unnecessary call to str.erase() here.
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
Xiretza
David Shah
Alberto Gonzalez
whitequark
Miodrag Milanović
Eddie Hung
Sahand Kashani
Marcelina Kościelnicka
N. Engelhardt
Henner Zeller
Claire Wolf
Jeff Wang