Commit Graph

4110 Commits

Author SHA1 Message Date
Martin Povišer 862f2fd705 proc_dlatch: Include `$bwmux` among considered mux cells 2024-02-08 00:08:50 +01:00
Jannis Harder bfd9cf63db Ignore $scopeinfo in opt_merge 2024-02-06 17:51:29 +01:00
Jannis Harder 8902fc94b6 Suport $scopeinfo in flatten and opt_clean 2024-02-06 17:51:29 +01:00
Miodrag Milanović 269c50f90e
Merge pull request #4130 from jix/hierarchy-defer-notop
hierarchy: Without a known top module, derive all deferred modules
2024-02-06 12:08:01 +01:00
Jannis Harder 0470cbb00d hierarchy: Without a known top module, derive all deferred modules
This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
2024-02-06 10:31:40 +01:00
Claire Xen 1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite
Add API to overwrite existing pass from plugin
2024-02-05 23:49:24 +01:00
N. Engelhardt f96e27ac14
Merge pull request #4123 from povik/clean-opt_clean
opt_clean: Add commentary, remove dead code
2024-02-05 15:08:34 +01:00
Catherine c7bf0e3b8f Add new `$check` cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
Jannis Harder e1a59ba80b async2sync, clk2fflogic: Add support for $check and $print cells 2024-02-01 20:10:39 +01:00
Jannis Harder 6c4902313b chformal: Support $check cells and add chformal -lower
This adds support for `$check` cells in chformal and adds a `-lower`
mode which converts `$check` cells into `$assert` etc. cells with a
`$print` cell to output the `$check` message.
2024-02-01 20:10:39 +01:00
Martin Povišer a84fa0a277 connect: Do interpret selection arguments
Instead of silently ignoring what would ordinarily be the selection
arguments to a pass, interpret those and mark the support in the help
message.
2024-02-01 10:28:36 +01:00
Martin Povišer 6c4bc5aae5
Merge pull request #4165 from phsauter/shiftadd-offset-fix
peepopt: handle offset too large in `shiftadd`
2024-01-31 13:47:39 +01:00
Philippe Sauter cbdf9b2f9c peepopt: handle empty src-attribute in shiftadd 2024-01-31 13:07:01 +01:00
Claire Xenia Wolf 4fa314c0bd Add API to overwrite existing pass from plugin
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-01-30 17:51:11 +01:00
Philippe Sauter 7f8b6dd982 peepopt: delete unnecessary comment in shiftadd 2024-01-30 09:51:21 +01:00
Martin Povišer 23c9828d70 opt_clean: Remove dead branch 2024-01-29 11:26:44 +01:00
Martin Povišer 7afc0696e2 opt_clean: Assert an impossible path isn't taken 2024-01-29 11:26:44 +01:00
Martin Povišer ec065186d3 opt_clean: Add commentary around wire cleaning, NFC 2024-01-29 11:26:44 +01:00
Philippe Sauter 68a9aa7c29 peepopt: handle offset too large in `shiftadd`
If the offset is larger than the signal itself,
meaning the signal is completely shifted out,
it tried to extract a negative amount of bits from the old signal.

This RTL pattern is suspicious since it is a complicated way of
arriving at a constant value, so we warn the user.
2024-01-26 16:44:30 +01:00
Jannis Harder 7c818d30f7 sim: Bring $print trigger/sampling semantics in line with FFs 2024-01-25 16:21:03 +01:00
Catherine 3d9e44d182 hierarchy: keep display statements, like formal assertions. 2024-01-22 10:09:22 +00:00
Stephen Tong b3e7390c0e
Fix typo in stat help 2024-01-21 16:32:05 -05:00
N. Engelhardt e1f4c5c9cb
Merge pull request #4133 from YosysHQ/show_color_proc
show: allow setting colors via selection on PROC boxes
2024-01-17 17:56:53 +01:00
Martin Povišer 6a7fad4dd9
Merge pull request #4132 from povik/opt_lut_ice40
opt_lut: Replace `-dlogic` with `-tech ice40`
2024-01-17 14:26:28 +01:00
N. Engelhardt fb4eeb1344 show: allow setting colors via selection on PROC boxes 2024-01-15 17:47:59 +01:00
Martin Povišer 149bcd88ad
Merge pull request #4026 from uis246/fix-format
Fix printf formats
2024-01-15 16:04:11 +01:00
Martin Povišer 568418b50b opt_lut: Replace `-dlogic` with `-tech ice40` 2024-01-15 12:35:21 +01:00
uis 5902b2826d Fix printf formats 2024-01-15 12:07:54 +01:00
Dag Lem acf916f654 Restore sim output from initial $display 2024-01-14 16:52:51 +01:00
Jannis Harder 57b4e16acd sim: Include $display output in JSON summary
This allows tools like SBY to capture the $display output independent
from anything else sim might log. Additionally it provides source and
hierarchy locations for everything printed.
2024-01-11 12:01:39 +01:00
N. Engelhardt 78541be4d8
Merge pull request #3971 from povik/equiv_simple-fixes
Fixes to `equiv_simple`
2023-12-18 16:31:02 +01:00
Jannis Harder cca12d9d9b
Merge pull request #4055 from povik/sim-hier-prints
sim: Print hierarchy for failed assertions
2023-12-11 16:55:36 +01:00
Jannis Harder 7b74caa5db peepopt: Fix padding for the peepopt_shiftmul_right pattern
The previous version could easily generate a large amount of padding
when the constant factor was significantly larger than the width of the
shift data input. This could lead to huge amounts of logic being
generated before then being optimized away at a huge performance and
memory cost.

Additionally and more critically, when the input width was not a
multiple of the constant factor, the input data was padded with 'x bits
to such a multiple before interspersing the 'x padding needed to align
the selectable windows to power-of-two offsets.

Such a final padding would not be correct for shifts besides $shiftx,
and the previous version did attempt to remove that final padding at the
end so that the native zero/sign/x-extension behavior of the shift cell
would be used, but since the last selectable window also got
power-of-two padding appended after the padding the code is trying to
remove got added, it did not actually fully remove it in some cases.

I changed the code to only add 'x padding between selectable windows,
leaving the last selectable window unpadded. This omits the need to add
final padding to a multiple of the constant factor in the first place.
In turn, that means the only 'x bits added are actually impossible to
select. As a side effect no padding is added when the constant factor is
equal to or larger than the width of the shift data input, also solving
the reported performance bug.

This fixes #4056
2023-12-06 18:35:44 +01:00
Martin Povišer 6581b5593c sim: Print hierarchy for failed assertions 2023-12-06 12:09:07 +01:00
Martin Povišer 16ea497d7c pmgen: Have a single make pattern
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
2023-12-05 18:30:13 +01:00
Martin Povišer d6566eb344 booth: Redo baseline architecture summation
Redo the summation logic: strive for some degree of balance on the
generated Wallace tree, emit an `$add` cell for the final summation.
2023-11-22 15:47:11 +01:00
Martin Povišer beb5cb55a5 booth: Expose `-lowpower` option 2023-11-22 15:29:59 +01:00
Martin Povišer 7005ea9411 booth: Revisit help 2023-11-22 15:29:59 +01:00
Martin Povišer 48b73be8c6 booth: Replace the default signed architecture
Generalize what was formerly the unsigned-only architecture to support
both signed and unsigned multiplication, use that as default, and set
aside the special low-power architecture that was formerly used for
signed multipliers.
2023-11-22 15:29:59 +01:00
Martin Povišer f50894d8bf booth: Drop extra decoder arguments 2023-11-22 15:29:54 +01:00
Martin Povišer 579f6bdc17 booth: Do not special-case bottom rows
Later on all the rows are cropped to the target size anyway, so there's
no harm in transitionally including extra top bits.
2023-11-22 15:12:15 +01:00
Martin Povišer da207cdce0 booth: Make less assumptions when aligning partial products 2023-11-22 15:12:15 +01:00
Martin Povišer 69e994ff75 booth: Clean unused FA index variable 2023-11-22 12:47:09 +01:00
Martin Povišer d8408b2350 booth: Move up signed quadrant 1 logic 2023-11-22 12:46:15 +01:00
Martin Povišer 8d33cc2fb6 booth: Refactor signed CPA 2023-11-22 12:46:15 +01:00
Martin Povišer 00e899f98d booth: Refactor signed multiplier full adders emission 2023-11-22 12:46:15 +01:00
N. Engelhardt 63cec22a0c
Merge pull request #3883 from phsauter/peepopt-shiftadd
peepopt: Add `shiftadd` pattern
2023-11-07 10:42:15 +01:00
phsauter 3618294bac peepopt: Add assert of consistent `shiftadd` data 2023-11-06 16:35:00 +01:00
Philippe Sauter b6df900bcc peepopt: Describe `shiftadd` rule in help message 2023-11-06 14:01:37 +01:00
phsauter 9ca57d9f13 peepopt: fix and refactor `shiftadd`
- moved all selection and filtering logic to the match block
- applied less-verbose code suggestions
- removed constraint on number of bits in shift-amount
- added check for possible wrap-arround in the operation
2023-11-06 14:01:37 +01:00
Philippe Sauter 72c6a01e67 peepopt: Add initial `shiftadd` pattern 2023-11-06 14:01:37 +01:00
N. Engelhardt 080da693d1 memory_libmap: update search order for attributes 2023-10-24 13:55:45 +02:00
N. Engelhardt 1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Lofty d21c464ae4
Merge pull request #3946 from rmlarsen/toposort
Speed up TopoSort by 2.7-3.3x.
2023-10-17 13:00:18 +01:00
Claire Xen a4951a3a97
Merge pull request #3986 from povik/sim-ui-fixes
Slightly improve `sim` UI
2023-10-16 16:54:05 +02:00
N. Engelhardt a2f59cf911
Merge pull request #3990 from zeldin/deterministic_scc 2023-10-16 16:51:54 +02:00
Martin Povišer d6d1cc705e pmgen: Fix sample syntax 2023-10-16 14:19:15 +02:00
Martin Povišer 660be4a31e peepopt: Describe rules in help message 2023-10-16 14:19:15 +02:00
Martin Povišer 5c0c8251c3 peepopt: Remove broken `-generate` option 2023-10-16 14:19:10 +02:00
Martin Povišer aa9b86aeec peepopt: Add left-shift 'shiftmul' variant
Add a separate shiftmul pattern to match on left shifts which implement
demuxing. This mirrors the right shift pattern matcher but is probably
best kept separate instead of merging the two into a single matcher.
In any case the diff of the two matchers should be easily readable.
2023-10-16 13:52:38 +02:00
Martin Povišer 038a5e1ed4 peepopt: Support shift amounts zero-padded from below
The `opt_expr` pass running before `peepopt` can interfere with the
detection of a shiftmul pattern due to some of the bottom bits of the
shift amount being replaced with constant zero. Extend the detection to
cover those situations as well.
2023-10-16 13:52:06 +02:00
Martin Povišer dd1a8ae49a peepopt: Try to use original wires 2023-10-16 13:52:06 +02:00
Martin Povišer bd8a81a907 peepopt: Clean up 'shiftmul' a bit
No functional change intended.
2023-10-16 13:52:06 +02:00
Martin Povišer a0c3be3aae peepopt: Drop unused 'initbits' code
Drop code that was once used by the 'dffmux' pattern but now is unused
after that pattern has been obsoleted by the 'opt_dff' pass.
2023-10-16 13:52:06 +02:00
N. Engelhardt 6c562c76bc fix handling right shifts 2023-10-12 11:46:09 +02:00
N. Engelhardt 3e22791810
Merge pull request #3975 from rmlarsen/optmerge 2023-10-09 17:05:19 +02:00
Marcus Comstedt 0ca39e233b scc: Use hashlib instead of STL for deterministic behaviour 2023-10-07 10:43:00 +02:00
Rasmus Munk Larsen 0a37c2a301 Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten.
Add back statement that inserts nodes in order in opt_expr.cc.
2023-10-05 17:01:42 -07:00
Martin Povišer c3fd88624a sim: Bail on processes
Instead of silently missimulating, error out when there are processes
found in the simulation hierarchy.
2023-10-05 19:25:17 +02:00
Martin Povišer a782b15aae sim: s/instanced/instantiated/ 2023-10-05 19:25:17 +02:00
Martin Povišer 6ac43e49bc sim: Change clocked read port suggestion to `memory_nordff`
`memory_nordff` has the advantage that it can be called just ahead of
the simulation step no matter whether the clocked read port has been
inferred or was explicitly instantiated in a flow.
2023-10-05 19:25:17 +02:00
Martin Povišer 0434f9d3d1 booth: Fix vacancy check when summing down result
In commit fedd12261 ("booth: Move away from explicit `Wire` pointers")
a bug was introduced when checking for vacant slots in arrays holding
some intermediate results. Non-wire SigBit values were taken to imply
a vacant slot, but actually a constant one can make its way into those
results, if the multiplier cell configuration is just right. Fix the
vacancy check to address the bug.
2023-10-04 23:21:40 +02:00
Rasmus Munk Larsen 57a2b4b0cd Explicitly use uint64_t as the type of fingerprint to avoid type mismatch with some compilers. 2023-10-03 15:02:02 -07:00
Rasmus Munk Larsen 8e0308b5e7 Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this. 2023-10-03 14:25:59 -07:00
Martin Povišer 1f1f43edd9 equiv_simple: Fix seed handling in non-short mode 2023-10-03 13:05:42 +02:00
Martin Povišer dbf11da50a equiv_simple: Do not special-case flip-flop types in cone expansion
If there's an asynchronous flip-flop type, it will be caught by not
having a synchronous SAT model later on. Otherwise we can support all
flip-flops.
2023-10-03 13:05:42 +02:00
Martin Povišer 26644ea779 equiv_simple: Drop hollow conditional
All the listed flip-flop types would be known cells, so the extra part
of the conditional is without effect.
2023-10-03 13:05:42 +02:00
Rasmus Munk Larsen bce984fa60 Speed up OptMergePass by 1.7x.
The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.
2023-10-02 15:57:18 -07:00
Rasmus Munk Larsen 1bbc12f389 Revert changes to techmap.cc. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen 67f1700486 Revert formatting changes. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen abd9c51963 Speed up simplemap_map by 11.6x by directly inserting the cell source attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on https://github.com/YosysHQ/yosys/pull/3959 2023-10-02 17:32:56 +01:00
Jannis Harder 8b42abee50
Merge pull request #3961 from jix/dft-fixes 2023-10-02 16:58:15 +02:00
Jannis Harder ecf09b9271
Merge pull request #3962 from jix/sim-noinitstate 2023-10-02 16:57:46 +02:00
N. Engelhardt dcb600ab81
Merge pull request #3938 from povik/booth-cleanup 2023-10-02 16:10:17 +02:00
Jannis Harder 5daa49bafb dft_tag: Fix size extending $x[n]or and $reduce_{or,bool}/$logic_not 2023-09-28 17:33:55 +02:00
Jannis Harder 7eaa4bcb46 sim: Add -noinitstate option and handle non-cosim initstate
This adds the -noinitstate option which is required to simulate
counterexamples to induction with yw-cosim. Also add handling for
$initstate cells for non-co-simulation.
2023-09-28 17:29:24 +02:00
Martin Povišer 6b70b3dbef booth: Fix assertion
Fix assertion to what it should be per Andy's comments.
2023-09-28 11:50:57 +02:00
N. Engelhardt 3319fdc46e show: use dot for wire aliases instead of BUF 2023-09-25 17:20:16 +02:00
Martin Povišer 91bcf81dbd booth: Note down debug prints are broken 2023-09-25 14:51:26 +02:00
Martin Povišer 7179e4f4b8 booth: Improve user interface 2023-09-25 14:50:41 +02:00
Martin Povišer cde2a0b926 booth: Make more use of appropriate helpers
Use the `addFa` helper, do not misuse `new_id` and make other changes
to the transformation code.
2023-09-25 14:50:41 +02:00
Martin Povišer 62302f601d booth: Remove more of unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer 30f8387b75 booth: Rewrite the main cell selection loop 2023-09-25 14:50:41 +02:00
Martin Povišer 986507f95f booth: Streamline the low-level circuit emission
For the basic single-bit operations, opt for gate cells (`$_AND_` etc.)
instead of the coarse cells (`$and` etc.). For the emission of cells
move to the conventional module methods (`module->addAndGate`) away
from the local helpers. While at it, touch on the surrounding code.
2023-09-25 14:50:41 +02:00
Martin Povišer cb05262fc4 booth: Remove now-unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer fedd12261f booth: Move away from explicit `Wire` pointers
To represent intermediate signals use the `SigBit`/`SigSpec` classes as
is customary in the Yosys codebase. Do not pass around `Wire` pointers
unless we have special reason to.
2023-09-25 14:50:41 +02:00
Rasmus Munk Larsen 9ed38bf9b6
Speed up the autoname pass by 3x. (#3945)
* Speed up the autoname pass by 2x. This is accomplished by only constructing IdString objects for plain strings that have a higher score.

* Defer creating IdStrings even further. This increases the speedup to 3x.
2023-09-21 09:46:49 +00:00
Rasmus Munk Larsen e0042bdff7 Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%. 2023-09-20 15:49:05 -07:00
Martin Povišer 54be4aca90
Merge pull request #3924 from andyfox-rushc/master
multpass -- create Booth Encoded multipliers for
2023-09-18 16:46:59 +02:00
Jannis Harder 62b4df4989 dft_tag: Implement `$overwrite_tag` and `$original_tag`
This does not correctly handle an `$overwrite_tag` on a module output,
but since we currently require the user to flatten the design for
cross-module dft, this cannot be observed from within the design, only
by manually inspecting the signals in the design.
2023-09-13 11:32:36 +02:00
Jannis Harder 46a35da28c Add `future` pass to resolve `$future_ff` cells 2023-09-13 11:32:36 +02:00
Jannis Harder 7a0c37b62d Initial dft_tag implementation
This is still missing a mode to rewrite $overwrite_tag and $original_tag
by injecting $set_tag and $get_tag in the right places. It's also
missing bit-precise propagation models for shifts and arithmetic and
requires the design to be flattened.
2023-09-13 11:32:36 +02:00
Miodrag Milanović 88ce47e4f0
Merge pull request #3892 from QuantamHD/dont_use
abc: Exposes dont_use flag in ABC
2023-09-12 14:58:44 +02:00
andyfox-rushc e4fe522767 MultPassWorker -> BoothPassWorker 2023-09-11 13:00:11 -07:00
andyfox-rushc eccc0ae6db Based passes/techmap/Makefile.inc changes on latest in yosys 2023-09-11 12:14:12 -07:00
andyfox-rushc a2c8e47295 multpass.cc -> booth.cc, added author/support contact info 2023-09-11 11:39:13 -07:00
Martin Povišer 5bef9b4e75
Merge pull request #3915 from povik/sim-print
sim: Add print support
2023-09-11 17:03:59 +02:00
andyfox-rushc 1b5287af59 cpa_carry array added to heap 2023-09-10 14:20:30 -07:00
andyfox-rushc 8d4b6c2f69 Switched arrays for signed multiplier construction to heap 2023-09-10 13:31:47 -07:00
andyfox-rushc d77fb81507 2d array -> 1d array in module generator 2023-09-10 12:45:36 -07:00
andyfox-rushc 6d29dc659b renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script 2023-09-08 15:34:56 -07:00
andyfox-rushc 411acc4a0a Fixed edge size cases for signed/unsigned booth generator 2023-09-08 13:41:31 -07:00
andyfox-rushc fedefa26bc multpass -- create Booth Encoded multipliers for 2023-09-06 16:35:17 -07:00
Jannis Harder e187fc915e xprop: Fix polarity errors and generate hdlnames
* Fixes a non-deterministic polarity error for $eqx/$nex cells
* Fixes a deterministic polarity error for $_NOR_ and $_ORNOT_ cells
* Generates hdlnames when xprop is run after flatten
2023-09-06 19:25:47 +02:00
Martin Povišer d4d951657f sim: Add `-assert` option to fail on failed assertions 2023-09-05 10:46:04 +02:00
Martin Povišer e995dddeaa abc: Warn about replacing undef bits 2023-09-05 10:45:30 +02:00
Martin Povišer c6566b660f memlib.md: Fix typo 2023-09-04 17:38:35 +02:00
Martin Povišer 3de84b959f memory_libmap: Tweak whitespace 2023-09-04 17:38:35 +02:00
Martin Povišer 50d117956c sim: Add print support 2023-09-04 17:12:38 +02:00
Miodrag Milanovic a8809989c4 ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech 2023-08-22 10:50:11 +02:00
Ethan Mahintorabi d525a41497
abc: Exposes dont_use flag in ABC
ABC's read_lib command has a dont_use
cell list that is configurable by the user.

This PR exposes that option to Yosys.

See
5405d4787a/src/map/scl/scl.c (L285)
for documentation on this option.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2023-08-15 20:03:46 +00:00
Charlotte 860e3e4056 proc_clean: only consider fully-defined switch operands too. 2023-08-12 02:46:31 +02:00
Charlotte bf84861fc2 proc_clean: only consider fully-defined case operands. 2023-08-12 02:46:31 +02:00
whitequark d51ecde8c2 clean: keep $print cells, since they have unmodelled side effects. 2023-08-11 04:46:52 +02:00
Martin Povišer ff3c7873f5 wreduce: Group reconnections
Group the reconnections, so that instead of producing

  connect $auto$wreduce.cc:455:run$24 [0] 1'0
  connect $auto$wreduce.cc:455:run$23 [31] 1'0
  connect $auto$wreduce.cc:455:run$23 [30] 1'0
  ... (40 more lines)

we produce

  connect $auto$wreduce.cc:461:run$23 [31:11] 21'000000000000000000000
  connect $auto$wreduce.cc:461:run$24 [31:10] 22'0000000000000000000000

.
2023-08-04 14:43:59 +01:00
Martin Povišer f8325f66b7 opt_expr: Fix 'signed X>=0' replacement for wide output ports
If the `$ge` cell we are replacing has wide output port, the upper bits
on the port should be driven to zero. That's not what a `$not` cell with
a single-bit input does. Instead opt for a `$logic_not` cell, which does
zero-pad its output.

Fixes #3867.
2023-08-01 13:50:12 +01:00
N. Engelhardt 43780c9812
Merge pull request #3838 from povik/various-cleanup 2023-07-24 16:24:23 +02:00
Catherine 6965abeefa abc, abc9_exe: fix build on WASI (and others with `const* stdout`).
C does not guarantee that stdout/stderr can be reassigned.
Most platforms do make them assignable, however musl and WASI that
is based on musl do not. WASI does not have `dup2()`; instead it has
its own non-portable version of it that can only assign to previously
allocated fds.

Update the stream redirection code so that it does the right thing
on WASI and other platforms.
2023-07-23 05:13:29 +01:00
Catherine 411b6e98cd abc, abc9_exe: respect `-q` when built with linked ABC.
This is mostly important for YoWASP builds, since those do not have
a way to build with external ABC (I prototyped it but for some reason
ABC always segfaults when built as an independent Wasm binary...)
2023-07-23 02:03:29 +01:00
Martin Povišer f5485b59a9 sim: Bail if there are blackboxes in simulation 2023-07-20 21:01:03 +01:00
Martin Povišer f0ae046c5a opt_share: Fix input confusion with ANDNOT, ORNOT gates
Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_`
gates when considering those for sharing. Unlike the input ports of the
other supported single-bit gates, those are not interchangeable.

Fixes #3848.
2023-07-20 20:58:52 +01:00
N. Engelhardt 2be5c0786f
Merge pull request #3826 from nakengelhardt/nak/mem_libmap_print_attr 2023-07-17 16:35:10 +02:00
Martin Povišer eb083c5d4b extract_counter: Update help and comments after UP/DOWN support
Commit fec7dc5c should have added support for up counters so update
the help and comments accordingly.
2023-07-10 12:45:03 +02:00
N. Engelhardt 57de249881 memory_libmap: print additional debug messages when no valid mapping is found 2023-07-06 18:54:32 +02:00
N. Engelhardt 14d50a176d
Merge pull request #3676 from nakengelhardt/dfflegalize_scratchpad_minarg 2023-07-03 17:15:21 +02:00
N. Engelhardt a6be7b4751 memory_libmap: add debug messages for some reasons for rejecting mappings 2023-06-29 14:08:31 +02:00
N. Engelhardt 7542146fc5 memory_libmap: print message about attributes forcing ram kind 2023-06-28 17:48:20 +02:00
Jannis Harder a07f8ac38a check: Also check for conflicts with constant drivers 2023-06-23 18:07:28 +02:00
Claire Xen 51e627686a
Merge pull request #3812 from charlottia/iterator-invalidation
proc_prune: avoid using invalidated iterator
2023-06-21 14:46:25 +02:00
Charlotte 63e4114233 proc_prune: avoid using invalidated iterator
An `std::vector<T>::reverse_iterator` stores the
`std::vector<T>::iterator` which points to the (forwards-ordered)
*following* item.  Thus while `vec.rbegin()` dereferences to the final
item of `vec`, the iterator it wraps (`vec.rbegin().base()`) is equal to
`vec.end()`.

In the remove case here, we advance `it` (backwards), erasing the item
we just advanced past by grabbing its (pre-increment) base
forward-iterator and subtracting 1.

The iterator maths here is obviously all OK, but the forward-iterator
that `it` wraps post-increment actually points to the item we just
removed.  That iterator was invalidated by the `erase()` call.

That this works anyway is (AFAICT) some combination of luck and/or
promises that aren't part of the C++ spec, but MSVC's debug iterator
support picks this up.

`erase()` returns the new iterator that follows the item just erased,
which happens to be the exact one we want our reverse-iterator to wrap
for the next loop; we get a fresh iterator to the same base, now without
the preceding item.
2023-06-21 19:53:08 +10:00
N. Engelhardt 9c7f0e7670 show: truncate very long module names 2023-06-20 12:53:56 +02:00
N. Engelhardt 22c9237716 show: escape angle brackets 2023-06-20 11:17:12 +02:00
N. Engelhardt 7c606bd5a3
Merge pull request #3791 from nakengelhardt/nak/show_attr_wires 2023-06-05 16:18:54 +02:00
N. Engelhardt 6f5d984bdb
Merge pull request #3778 from jix/yw_clk2fflogic 2023-06-05 16:15:04 +02:00
N. Engelhardt 0707b911c7 show: add -viewer none option 2023-06-01 11:00:07 +02:00
N. Engelhardt 4b986c9c65 fix wire color after BUF 2023-05-31 17:38:46 +02:00
N. Engelhardt 26555a998d show -colorattr: extend colors to arrows when wires have attribute 2023-05-26 17:18:21 +02:00
Eddie Hung ec8d7b1c68 abc9_ops -prep_hier to unmap entire module 2023-05-25 18:42:08 +01:00
Jannis Harder e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses
This makes clk2fflogic add an attr to $ff cells that carry the state of
the emulated async FF. The $ff output doesn't have any async updates
that happened in the current cycle, but the $ff input does, so the $ff
input corresponds to the async FF's output in the original design.

Hence this patch also makes the following changes to passes besides
clk2fflogic (but only for FFs with the clk2fflogic attr set):

  * opt_clean treats the input as a register name (instead of the
    output)

  * rename -witness ensures that the input has a public name

  * the formal backends (smt2, btor, aiger) will use the input's
    name for the initial state of the FF in witness files

  * when sim reads a yw witness that assigns an initial value to the
    input signal, the state update is redirected to the output

This ensures that yosys witness files for clk2fflogic designs have
useful and stable public signal names. It also makes it possible to
simulate a clk2fflogic witness on the original design (with some
limitations when the original design is already using $ff cells).

It might seem like setting the output of a clk2fflogic FF to update the
input's initial value might not work in general, but it works fine for
these reasons:

  * Witnesses for FFs are only present in the initial cycle, so we do
    not care about any later cycles.

  * The logic that clk2fflogic generates loops the output of the
    genreated FF back to the input, with muxes in between to apply any
    edge or level sensitive updates. So when there are no active updates
    in the current gclk cycle, there is a combinational path from the
    output back to the input.

  * The logic clk2fflogic generates makes sure that an edge sensitive
    update cannot be active in the first cycle (i.e. the past initial
    value is assumed to be whatever it needs to be to avoid an edge).

  * When a level sensitive update is active in the first gclk cycle, it
    is actively driving the output for the whole gclk cycle, so ignoring
    any witness initialization is the correct behavior.
2023-05-25 12:48:02 +02:00
Jannis Harder 7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization 2023-05-25 12:46:16 +02:00