yosys

Commit Graph

Author	SHA1	Message	Date
Krystine Sherwin	aef9921fc9	Tidying TODOs	2023-12-08 09:50:10 +13:00
Krystine Sherwin	1e3b90ae56	Removing typical phases doc Moved remaining content into relevant places. Added `load_design.rst` to more scripting. Split fsm handling and abc out of optimization passes. Also moved things around to match the general flow previously described. Changed generic `synth` for `prep` instead.	2023-12-07 17:14:21 +13:00
Krystine Sherwin	f9ce3d1c26	WIP merging synth phases with example Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`. Also updating the counter example to match. Aims to reduce redundancy, and simplify the getting started section. Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).	2023-12-07 13:04:46 +13:00

Author

SHA1

Message

Date

Krystine Sherwin

aef9921fc9

Tidying TODOs

2023-12-08 09:50:10 +13:00

Krystine Sherwin

1e3b90ae56

Removing typical phases doc

Moved remaining content into relevant places.
Added `load_design.rst` to more scripting.
Split fsm handling and abc out of optimization passes. Also moved things around to match the general flow previously described.
Changed generic `synth` for `prep` instead.

2023-12-07 17:14:21 +13:00

Krystine Sherwin

f9ce3d1c26

WIP merging synth phases with example

Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`.
Also updating the counter example to match.

Aims to reduce redundancy, and simplify the getting started section.
Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).

2023-12-07 13:04:46 +13:00

3 Commits