riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,218 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Miodrag Milanovic 83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00