Commit Graph

6 Commits

Author SHA1 Message Date
Krystine Sherwin e2e7065590
Docs: some restructure of advanced section
- Filling out index descriptions for `using_yosys` and `using_yosys/synthesis`.
- To discourage skipping over these index pages, the toctree in
  `using_yosys/index` is hidden and instead has inline links to the two
  subsections.
- Tidying todos.
- Moves technology mapping to `techmap_synth`, leaving the techmap by example in
  the internals section. `yosys_flows` gets split up, with the coarse-grain
  intro replaced by `synthesis/index`, the extract pass moving to
  `synthesis/extract` and model checking to `more_scripting/model_checking`.
2024-01-26 13:08:22 +13:00
Krystine Sherwin a33b1b6059
More work on example_synth
Added highlighting in (most) schematics.
Written down to end of coarse-grain, with a couple of TODOs for filling in gaps.
Includes `techmap_synth.rst` stub.
2023-12-18 17:49:15 +13:00
Krystine Sherwin 3a153f99db
Add cell_libs.rst
Updates code examples, removing `counter_outputs.ys` in favour of a single script.  Also adds a .gitignore for the output file `synth.v`.
`example_synth.rst` still pending updated example.
2023-12-14 10:08:46 +13:00
Krystine Sherwin e34a25ea27
TODOs
Blocking tasks are now capital TODO (compared to non-blocking todo).
Updated some of the todos.
Added note about which intel synth does which families.
Rename extended Yosys universe to Yosys family.
Added brief text to landing page, and also a note about the restructure and where to find old docs.
Moved todolist above ToC in preparation for disabling it in the config (so that it doesn't need it's own header).

Fixed pdf build, was previously breaking on trying to include the svg badges.
2023-12-12 12:05:45 +13:00
Krystine Sherwin 1e3b90ae56
Removing typical phases doc
Moved remaining content into relevant places.
Added `load_design.rst` to more scripting.
Split fsm handling and abc out of optimization passes. Also moved things around to match the general flow previously described.
Changed generic `synth` for `prep` instead.
2023-12-07 17:14:21 +13:00
Krystine Sherwin f9ce3d1c26
WIP merging synth phases with example
Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`.
Also updating the counter example to match.

Aims to reduce redundancy, and simplify the getting started section.
Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).
2023-12-07 13:04:46 +13:00