riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,133 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

562 Commits

Author SHA1 Message Date
clairexen 22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s 
Allow %0s $display format specifier
 2020-08-18 17:39:01 +02:00
clairexen 4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish 
Propagate const_fold through generate blocks and branches
 2020-08-18 17:38:07 +02:00
clairexen a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock 
Fix generate scoping issues
 2020-08-18 17:37:11 +02:00
Claire Wolf 7f767bf2b7 Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-08-18 17:29:49 +02:00
clairexen 5ee9349647
Merge pull request #2281 from zachjs/const-real 
Allow reals as constant function parameters
 2020-08-18 17:22:20 +02:00
Zachary Snow 2ee0b8ebea Propagate const_fold through generate blocks and branches 2020-08-09 17:21:08 -04:00
Zachary Snow 96ec9acf84 Allow %0s $display format specifier 2020-08-09 17:19:49 -04:00
Zachary Snow c3e95eb1ab Fix generate scoping issues 
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456
 2020-07-31 20:32:47 -06:00
clairexen 45e96d5d87
Merge pull request #2301 from zachjs/for-loop-errors 
Clearer for loop error messages
 2020-07-28 14:07:26 +02:00
Zachary Snow 58da181af9 Clearer for loop error messages 2020-07-25 10:37:16 -06:00
Zachary Snow f69daf4830 Allow blocks with declarations within constant functions 2020-07-25 10:16:12 -06:00
Zachary Snow 59c4ad8ed3 Avoid generating wires for function args which are constant 2020-07-24 21:18:24 -06:00
Zachary Snow f285f7b769 Allow reals as constant function parameters 2020-07-19 20:27:09 -06:00
Claire Wolf f9ed09423e Add AST_EDGE support to AstNode::detect_latch(), fixes #2241 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-10 18:41:13 +02:00
clairexen 8ce4f8790e
Merge pull request #2179 from splhack/static-cast 
Support SystemVerilog Static Cast
 2020-07-01 16:40:20 +02:00
Zachary Snow 27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Kazuki Sakamoto 429d37ff41 static cast: simplify 2020-06-19 19:09:43 -07:00
Kazuki Sakamoto 185bbbe681 static cast: support changing size and signedness 
Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)

Fix #535
 2020-06-19 17:39:20 -07:00
whitequark 118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
clairexen 5c426d2bff
Merge pull request #2112 from YosysHQ/claire/fix2040 
Add latch detection for use_case_method in part-select write
 2020-06-09 18:27:59 +02:00
Peter Crozier 76c499db71 Support packed arrays in struct/union. 2020-06-07 18:33:11 +01:00
Claire Wolf 7ad0c49905 Add latch detection for use_case_method in part-select write, fixes #2040 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 23:25:59 +02:00
clairexen 352731df4e
Merge pull request #2041 from PeterCrozier/struct 
Implementation of  SV structs.
 2020-06-04 18:26:07 +02:00
whitequark 3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire 
Preserve 'signed'-ness of a verilog wire through RTLIL
 2020-06-04 11:23:06 +00:00
Peter Crozier 0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
clairexen 0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 
ast/simplify: don't bitblast async ROMs declared as `logic`
 2020-05-29 16:52:11 +02:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Claire Wolf ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 
ast: swap range regardless of range_left >= 0
 2020-05-14 18:06:18 +02:00
Peter Crozier f482c9c016 Generalise structs and add support for packed unions. 2020-05-12 14:25:33 +01:00
Peter Crozier 0b6b47ca67 Implement SV structs. 2020-05-08 14:40:49 +01:00
whitequark ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs 
Avoid switch fall-through warnings
 2020-05-08 05:30:32 +00:00
Claire Wolf 0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990 
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
 2020-05-07 18:11:48 +02:00
Xiretza 695150b037
Add YS_FALLTHROUGH macro to mark case fall-through 
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
 2020-05-07 13:39:34 +02:00
Eddie Hung 283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup 
frontend: cleanup to use more ID::*, more dict<> instead of map<>
 2020-05-05 07:59:40 -07:00
whitequark 66d0ed2bcc ast/simplify: don't bitblast async ROMs declared as `logic`. 
Fixes #2020.
 2020-05-05 04:16:59 +00:00
Eddie Hung e936ac61ea ast: swap range regardless of range_left >= 0 2020-05-04 12:18:20 -07:00
Eddie Hung 22bf22fab4 frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
Eddie Hung eca9fc01a7 verilog: set src attribute for primitives 2020-05-04 10:22:05 -07:00
Eddie Hung 584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations 
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
 2020-05-04 08:58:50 -07:00
Claire Wolf 88185f8959 Fix handling of signed indices in bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf 589ed2d970 Add AST_SELFSZ and improve handling of bit slices 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf bbbce0d1c5 Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Alberto Gonzalez b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`. 2020-05-01 07:17:27 +00:00
Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL 
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
 2020-04-27 09:44:24 -07:00
Claire Wolf 9f1fb11b1d Clear current_scope when done with RTLIL generation, fixes #1837 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-22 14:51:20 +02:00
Marcelina Kościelnicka 06a344efcb ilang, ast: Store parameter order and default value information. 
Fixes #1819, #1820.
 2020-04-21 19:09:00 +02:00
Claire Wolf 9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite 
Improved rewrite code for writing to bit slice
 2020-04-21 18:46:52 +02:00
whitequark abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name 
ast, rpc: record original name of $paramod\* as \hdlname attribute
 2020-04-21 01:43:20 +00:00
Claire Wolf 35990b95ec Extend support for format strings in Verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-18 14:08:51 +02:00