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13852 Commits

Author SHA1 Message Date
N. Engelhardt 7f08a298a4
Merge pull request #4542 from YosysHQ/krys/rtd 
Local readthedocs
 2024-08-19 10:04:38 +02:00
David Lanzendörfer d1b767ea8b Adding missing to Gowin tech files 
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip
design for my Sipeed Tang FPGA fails.
 2024-08-18 19:38:31 +01:00
NachtSpyder04 aa60255e0e update help messages that went beyond line length limit 2024-08-18 20:27:35 +05:30
Saish Karole 34aabd56cc
Apply suggestions from code review 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-08-18 20:12:53 +05:30
Saish Karole d80d4dc51c
[Docs]:Add new cell type help messages (#1) 
* add shift operators description

* update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators
 2024-08-17 15:47:00 +05:30
github-actions[bot] 5fb3c0b1d9 Bump version 2024-08-17 00:17:44 +00:00
KrystalDelusion 3dd32d741a Stop unconditionally building abc 
_What are the reasons/motivation for this change?_
abc builds unconditional because `check-git-abc` is a phony prerequisite and therefore always runs, and since it always runs it will always trigger abc to rebuild.

_Explain how this is achieved._
Convert `check-git-abc` to an order-only prerequisite.  It still runs as before, but no longer triggers yosys-abc to rebuild when it does.

_If applicable, please suggest to reviewers how they can test the change._
 2024-08-17 11:04:17 +12:00
Krystine Sherwin 7bd3c7b968
Fix test-verific.yml 2024-08-16 10:43:51 +12:00
Krystine Sherwin 3b63ab07ae
docs: Build RTD artifacts directly 
Use rtds-action instead of yosys-cmd-ref repo.
Add rtds_action to docs configuration.
Add `.readthedocs.yaml`.
Update `DOCS_USAGE_` make target to be able to use pre-generated executables without forcing a remake.
 2024-08-16 10:43:51 +12:00
Miodrag Milanović ceba889641
Merge pull request #4540 from YosysHQ/clang-11 
Replace test-compile (ubuntu-22.04, clang-11)
 2024-08-15 17:39:42 +02:00
github-actions[bot] 1eaf4e0790 Bump version 2024-08-15 00:17:57 +00:00
Krystine Sherwin d709177770
test-compile: Downgrade to focal 2024-08-15 09:44:20 +12:00
Martin Povišer a854903ff0
Merge pull request #4537 from povik/libparse-cleanup 
Liberty parsing cleanup
 2024-08-14 18:24:51 +02:00
Martin Povišer ab5d6b06b4 read_liberty: Fix omitted helper change 2024-08-13 20:12:38 +02:00
Martin Povišer 309d80885b read_liberty: Use available gate creation helpers 2024-08-13 18:47:36 +02:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Martin Povišer c35f5e379c Extend liberty tests 2024-08-13 18:47:36 +02:00
Martin Povišer 78382eaa6f libparse: Adjust whitespace 2024-08-13 18:47:36 +02:00
github-actions[bot] 4b9f452735 Bump version 2024-08-13 00:19:11 +00:00
Martin Povišer 8ce6219a34
Merge pull request #4528 from povik/bump-abc 
Bump ABC
 2024-08-12 15:53:16 +02:00
Martin Povišer bcb995b506 Sync with yosys-experimental branch 2024-08-08 17:33:54 +02:00
github-actions[bot] 77b2ae2e39 Bump version 2024-08-08 00:18:08 +00:00
Martin Povišer 4b5beb635f Pull ABC fix 2024-08-07 17:31:34 +02:00
Martin Povišer ebffe37e4c Bump ABC 2024-08-07 15:54:03 +02:00
Martin Povišer b1569de537
Merge pull request #4527 from povik/exec-newline 
exec: Add missing newline
 2024-08-07 13:04:48 +02:00
Martin Povišer 4c3203866f exec: Add missing newline 2024-08-07 13:02:00 +02:00
github-actions[bot] 669f8b18f0 Bump version 2024-08-07 00:18:20 +00:00
Miodrag Milanovic d08bf671b2 Next dev cycle 2024-08-06 09:48:35 +02:00
Miodrag Milanovic 80ba43d262 Release version 0.44 2024-08-06 09:42:28 +02:00
Miodrag Milanović e5d8505349
Merge pull request #4523 from YosysHQ/emil/no-lto-lld 
Makefile: no LTO and lld by default
 2024-08-06 09:08:09 +02:00
github-actions[bot] d2b5788674 Bump version 2024-08-06 00:18:14 +00:00
Emil J. Tywoniak eeecb54532 Makefile: no LTO and lld by default 2024-08-05 19:28:09 +02:00
N. Engelhardt 01b99972b4
Merge pull request #4518 from YosysHQ/micko/sim_signal_names 
Set ranges on exported wires in VCD and FST
 2024-08-05 15:03:59 +02:00
Miodrag Milanovic 6d98418f3d Set ranges on exported wires in VCD and FST 2024-08-02 15:23:00 +02:00
Roland Coeurjoly 7e34142965 Run nix build also on macos. Build with more logs 2024-07-30 22:47:30 +02:00
github-actions[bot] c788484679 Bump version 2024-07-30 00:18:19 +00:00
Miodrag Milanović 3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Emil J 92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy 
cost: add keep_hierarchy pass with min_cost argument
 2024-07-29 16:33:08 +02:00
Miodrag Milanovic 405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
N. Engelhardt 7c3666ff68
Merge pull request #4505 from YosysHQ/micko/ext_register 
Initialize extensions when Verific pass is registered
 2024-07-29 15:23:31 +02:00
Emil J e21dd292fc
Merge pull request #4502 from YosysHQ/emil/build-opt-levels 
Release build configuration improvements
 2024-07-29 15:13:52 +02:00
Emil J. Tywoniak af0c2fa659 Brewfile: add llvm for lld 2024-07-29 15:13:24 +02:00
Emil J 051d83205d
Merge pull request #4471 from georgerennie/hashlib_primes 
hashlib: Add some more primes
 2024-07-29 15:10:22 +02:00
Martin Povišer 61ae9f4e07
Merge pull request #4514 from YosysHQ/emil/proc_rom-src-test-2 
proc_rom: test src attribute on memories
 2024-07-29 13:58:19 +02:00
Emil J. Tywoniak 4b29f64142 cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter 2024-07-29 10:26:02 +02:00
Emil J 49eaa108a5
Merge pull request #4425 from YosysHQ/emil/doc-sigmap 
sigmap: comments
 2024-07-29 10:18:44 +02:00
Emil J. Tywoniak 01fd72520f proc_rom: test src attribute on memories 2024-07-29 10:13:45 +02:00
github-actions[bot] 960bca0196 Bump version 2024-07-27 00:17:35 +00:00
Martin Povišer ced1313193
Merge pull request #4510 from JamesTimothyMeech/patch-1 
Update interactive_investigation.rst
 2024-07-26 15:17:57 +02:00