riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,304 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

25 Commits

Author SHA1 Message Date
Miodrag Milanovic ee3162c58d Add PLL and EBR related primitives 2023-04-10 12:39:09 +02:00
Miodrag Milanovic d5a405d3b4 Added proper simulation model for CCU2D 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 6e4c1675e7 Generate TRELLIS_DPR16X4 for lutram 2023-04-06 09:10:14 +02:00
Miodrag Milanovic 6e12da3956 machxo2: Initial support for carry chains (CCU2D) 2023-04-06 09:10:14 +02:00
Miodrag Milanovic ff9f1fb86e Start unification effort for machxo2 and ecp5 2023-03-20 09:58:41 +01:00
Marcelina Kościelnicka 2dcb0797f0 machxo2: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
Marcelina Kościelnicka 15b0d717ed iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
William D. Jones ae07298a6b machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
William D. Jones e3974809ec machxo2: Add DCCA and DCMA blackbox primitives. 2021-02-23 17:39:58 +01:00
William D. Jones a1ea1430b6 machxo2: Fix reversed interpretation of REG_SD config bits. 2021-02-23 17:39:58 +01:00
William D. Jones 4e9def23de machxo2: Tristate is active-low. 2021-02-23 17:39:58 +01:00
William D. Jones 8b14152506 machxo2: Fix typos in FACADE_FF sim model. 2021-02-23 17:39:58 +01:00
William D. Jones 8348c45e4f machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. 2021-02-23 17:39:58 +01:00
William D. Jones 3674eb34d4 machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells. 2021-02-23 17:39:58 +01:00
William D. Jones 124780ecd9 machxo2: Add missing OSCH oscillator primitive. 2021-02-23 17:39:58 +01:00
William D. Jones 3697f351d5 machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE. 2021-02-23 17:39:58 +01:00
William D. Jones f07b8eb606 machxo2: Fix cells_sim typo where OFX1 was multiply-driven. 2021-02-23 17:39:58 +01:00
William D. Jones 03cbf1327d machxo2: Add initial value for Q in FACADE_FF. 2021-02-23 17:39:58 +01:00
William D. Jones 0364ded385 machxo2: Add FACADE_IO simulation model. More comments on models. 2021-02-23 17:39:58 +01:00
William D. Jones 1b703d3f03 machxo2: Add FACADE_SLICE simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones cc52eb53cd machxo2: Improve FACADE_FF simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones 427fed23ee machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. 2021-02-23 17:39:58 +01:00
William D. Jones 044393b990 machxo2: Fix more oversights in machxo2 models. logic.ys test passes. 2021-02-23 17:39:58 +01:00
William D. Jones b87f6a0906 machxo2: Fix typos. test/arch/run-test.sh passes. 2021-02-23 17:39:58 +01:00
William D. Jones 88c8f81260 machxo2: Create basic techlibs and synth_machxo2 pass. 2021-02-23 17:39:58 +01:00