Miodrag Milanovic
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9bd9db56c8
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Unify verilog style
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2019-10-18 12:50:24 +02:00 |
Miodrag Milanovic
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12383f37b2
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Common memory test now shared
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2019-10-18 12:33:35 +02:00 |
Miodrag Milanovic
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477702b8c9
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Remove not needed tests
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2019-10-18 12:20:35 +02:00 |
Miodrag Milanovic
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5603595e5c
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Share common tests
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2019-10-18 12:19:59 +02:00 |
Miodrag Milanovic
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ab98f2dccf
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fix yosys path
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2019-10-18 11:18:53 +02:00 |
Miodrag Milanovic
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56f9482675
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Fix path to yosys
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2019-10-18 11:12:03 +02:00 |
Miodrag Milanovic
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c2ec7ca703
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
Miodrag Milanovic
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3c41599ee1
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Add async2sync
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2019-10-18 11:00:27 +02:00 |
Miodrag Milanović
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0568920d79
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Merge pull request #1435 from YosysHQ/mmicko/efinix
Add tests for Efinix architecture (contd)
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2019-10-18 10:54:35 +02:00 |
Miodrag Milanović
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b4d7650548
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Merge branch 'master' into mmicko/efinix
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2019-10-18 10:54:28 +02:00 |
Miodrag Milanović
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ab4899a2d0
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Merge pull request #1434 from YosysHQ/mmicko/anlogic
Add tests for Anlogic architecture (contd)
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2019-10-18 10:54:04 +02:00 |
Miodrag Milanović
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66fca65b58
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Merge branch 'master' into mmicko/anlogic
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2019-10-18 10:53:56 +02:00 |
Miodrag Milanović
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5ffb0053ec
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Merge pull request #1421 from YosysHQ/eddie/pr1352
Add tests for ECP5 architecture (contd)
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2019-10-18 10:53:34 +02:00 |
Miodrag Milanović
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0b0b0cc0d9
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Merge branch 'master' into eddie/pr1352
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2019-10-18 10:52:50 +02:00 |
Miodrag Milanović
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e0a67fce12
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Merge pull request #1420 from YosysHQ/eddie/pr1363
Add tests for Xilinx architecture (contd)
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2019-10-18 10:51:32 +02:00 |
Miodrag Milanovic
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b659082e4a
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hierarchy - proc reorder
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2019-10-18 09:13:06 +02:00 |
Miodrag Milanovic
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46af9a0ff7
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hierarchy - proc reorder
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2019-10-18 09:06:43 +02:00 |
Miodrag Milanovic
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0d60902fd9
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hierarchy - proc reorder
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2019-10-18 09:04:02 +02:00 |
Miodrag Milanovic
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e6ad714d20
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hierarchy - proc reorder
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2019-10-18 08:06:57 +02:00 |
N. Engelhardt
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3b405d985e
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Call memory_dff before DSP mapping to reserve registers (fixes #1447)
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2019-10-17 21:33:54 +02:00 |
Miodrag Milanovic
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980df499ab
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Make equivalence work with latest master
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2019-10-17 17:24:53 +02:00 |
Miodrag Milanovic
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b2f0d75807
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remove not needed top module
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2019-10-17 17:11:11 +02:00 |
Miodrag Milanovic
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1a399c6456
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remove not needed top module
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2019-10-17 17:11:11 +02:00 |
Miodrag Milanovic
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a198bcdd4f
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split muxes synth per type
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2019-10-17 17:11:11 +02:00 |
Miodrag Milanovic
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36af102801
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Test dffs separetely
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2019-10-17 17:11:11 +02:00 |
Miodrag Milanovic
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487b38b124
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Split latches into separete tests
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2019-10-17 17:11:11 +02:00 |
Miodrag Milanovic
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fba6229718
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Fix formatting
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2019-10-17 17:10:42 +02:00 |
Miodrag Milanovic
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53bc499a90
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Clean verilog code from not used define block
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2019-10-17 17:10:42 +02:00 |
Miodrag Milanovic
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d37cd267a5
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Removed alu and div_mod test as agreed, ignore generated files
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2019-10-17 17:10:42 +02:00 |
Miodrag Milanovic
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a7fbc8c3fe
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Test per flip-flop type
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2019-10-17 17:10:42 +02:00 |
Eddie Hung
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3b44084320
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Add -assert
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2019-10-17 17:10:42 +02:00 |
Eddie Hung
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8422ad3e3a
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Use built-in async2sync call as per #1417
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2019-10-17 17:10:42 +02:00 |
Eddie Hung
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5b7bc3ab85
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Update mul test to DSP48E1
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2019-10-17 17:10:02 +02:00 |
Eddie Hung
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08bd1816e3
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Update area for div_mod
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2019-10-17 17:10:02 +02:00 |
Eddie Hung
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a12801843b
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Add comment for lack of tristate logic pointing to #1225
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2019-10-17 17:10:02 +02:00 |
Eddie Hung
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eded90b6b4
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Move $x to end as 7f0eec8
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2019-10-17 17:10:02 +02:00 |
SergeyDegtyar
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305672170b
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adffs test update (equiv_opt -multiclock)
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2019-10-17 17:10:02 +02:00 |
Sergey
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bb70eb977d
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Fix div_mod test
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2019-10-17 17:10:02 +02:00 |
Sergey
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68f9239c57
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Fix div_mod test
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2019-10-17 17:10:02 +02:00 |
Sergey
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df6d0b95da
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Fix div_mod test
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2019-10-17 17:10:02 +02:00 |
Sergey
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c340d54657
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Fix div_mod test
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2019-10-17 17:10:02 +02:00 |
Sergey
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205f52ffe5
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Fix div_mod test
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2019-10-17 17:10:02 +02:00 |
Sergey
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df7fe40529
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Fix div_mod test
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2019-10-17 17:10:02 +02:00 |
SergeyDegtyar
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7bc8f0c2e2
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Add comment with expected behavior for latches,tribuf tests;Update adffs test
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2019-10-17 17:10:02 +02:00 |
SergeyDegtyar
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489444bcba
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Fix latches.ys test
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2019-10-17 17:10:02 +02:00 |
SergeyDegtyar
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6331fa5b02
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Remove xilinx_ug901 tests (will be moved to yosys-tests)
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2019-10-17 17:10:02 +02:00 |
SergeyDegtyar
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757c476f62
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Add smoke tests to tests/xilinx
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2019-10-17 17:10:02 +02:00 |
SergeyDegtyar
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ca7a58bcc8
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Add comments for unproven cells.
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2019-10-17 17:08:38 +02:00 |
SergeyDegtyar
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2ae7dec530
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Add tests for Xilinx UG901 examples
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2019-10-17 17:08:38 +02:00 |
Clifford Wolf
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0d037bf9d8
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Merge pull request #1450 from YosysHQ/clifford/fixdffmux
Fix handling of init attributes in peepopt dffmux pattern
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2019-10-16 14:44:38 +02:00 |