riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,251 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Zachary Snow 90bb47d181 verilog: fix const func eval with upto variables 2022-02-11 21:01:51 +01:00